From patchwork Sun Jul 14 16:23:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 1131752 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45msTT6sK2z9sNT for ; Mon, 15 Jul 2019 02:25:33 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id ABFE6C21E0D; Sun, 14 Jul 2019 16:24:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E6FF2C21D74; Sun, 14 Jul 2019 16:24:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E6275C21BE5; Sun, 14 Jul 2019 16:24:05 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lists.denx.de (Postfix) with ESMTPS id 2C566C21C29 for ; Sun, 14 Jul 2019 16:24:05 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Jul 2019 09:24:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,491,1557212400"; d="scan'208";a="318472056" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga004.jf.intel.com with ESMTP; 14 Jul 2019 09:24:01 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 752862FD; Sun, 14 Jul 2019 19:24:00 +0300 (EEST) From: Andy Shevchenko To: Simon Glass , Bin Meng , u-boot@lists.denx.de Date: Sun, 14 Jul 2019 19:23:59 +0300 Message-Id: <20190714162359.56390-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190714162359.56390-1-andriy.shevchenko@linux.intel.com> References: <20190714162359.56390-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Cc: Andy Shevchenko Subject: [U-Boot] [PATCH v2 4/4] x86: tangier: Populate CSRT for shared DMA controller X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Intel Tangier has a shared DMA controller that, according to Microsoft spec, has to be presented in CSRT table. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- arch/x86/cpu/tangier/acpi.c | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 0e4f961c53..61b2642aa9 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -68,6 +68,44 @@ u32 acpi_fill_mcfg(u32 current) return current; } +static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp) +{ + struct acpi_csrt_shared_info *si = (struct acpi_csrt_shared_info *)&grp[1]; + + /* Fill the Resource Group with Shared Information attached */ + memset(grp, 0, sizeof(*grp)); + grp->shared_info_length = sizeof(struct acpi_csrt_shared_info); + grp->length = sizeof(struct acpi_csrt_group) + grp->shared_info_length; + /* TODO: All values below should come from U-Boot DT somehow */ + sprintf((char *)&grp->vendor_id, "%04X", 0x8086); + grp->device_id = 0x11a2; + + /* Fill the Resource Group Shared Information */ + memset(si, 0, sizeof(*si)); + si->major_version = 1; + si->minor_version = 0; + /* TODO: All values below should come from U-Boot DT somehow */ + si->mmio_base_low = 0xff192000; + si->mmio_base_high = 0; + si->gsi_interrupt = 32; + si->interrupt_polarity = 1; + si->interrupt_mode = 0; + si->num_channels = 8; + si->dma_address_width = 32; + si->base_request_line = 0; + si->num_handshake_signals = 16; + si->max_block_size = 0x20000; + + return grp->length; +} + +u32 acpi_fill_csrt(u32 current) +{ + current += acpi_fill_csrt_dma((struct acpi_csrt_group *)current); + + return current; +} + void acpi_create_gnvs(struct acpi_global_nvs *gnvs) { struct udevice *dev;