From patchwork Fri Jul 12 10:50:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Opaniuk X-Patchwork-Id: 1131274 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pXimlYvD"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45lV8C3DKnz9s8m for ; Fri, 12 Jul 2019 20:50:51 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 25D5FC21DDC; Fri, 12 Jul 2019 10:50:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B6D77C21DA6; Fri, 12 Jul 2019 10:50:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C75C4C21DEC; Fri, 12 Jul 2019 10:50:39 +0000 (UTC) Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by lists.denx.de (Postfix) with ESMTPS id CB260C21DC1 for ; Fri, 12 Jul 2019 10:50:38 +0000 (UTC) Received: by mail-wr1-f68.google.com with SMTP id p17so9461354wrf.11 for ; Fri, 12 Jul 2019 03:50:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ebJ2dMSk5yBqF1c/74yVDwpSbcMe2RLVgn0Rfiv8Boo=; b=pXimlYvDzlDpxmSMBENVXDUwgvrgsNKKbVzDRnorUYqFJvO0AiPL5i92gKoNidXZ0y aP9GnK4naG3ZVpGHwF/7biOYaC1rFTvx1mZHZMJkDkPohAD2h8VsqagDwPbtyKrQnpKp Wig7XMSv2osQkt+nq9kN7iFDKttFTE5vHqrEAmfd+WMhOwNtvWkKPbX0zF5SQRJxzjGi +vM/7S0QLzERI/j8Sjum4rZJZEubYSPry/1eBfL6d8p4SDBcpq5aP1sH5c7c/cBwHxkq S7C5emY8gTeMlvh5Eh0uMQ7Jy/hE3/mA0HMK8lKxNp0PZnPhEGba93P986mVT71ATYQe zSWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ebJ2dMSk5yBqF1c/74yVDwpSbcMe2RLVgn0Rfiv8Boo=; b=swIk+rRfTA4BwiekK6/+ZqXvoisjCPH/OkCTRC/OjpcJH75/LMF6Rhr+e9dQSuVbBW vkuAk2UwGZlNgfsT9zedQXpQBwsrt3tXswKIxxOs64J0YiD69dCoI6llQkZVOqfJTsUM CGk7Pgsr2Y/h5gIJdxQTeLn3MISYvJSwkivuIbmo/K5PXgiov/543LnbseGNU9nbsGnb 2PM/DmEc2s34GK1l3QQrfOV84AS9m0VdrVCQQE9y2FmLdo8IFAMdZ3mMHFeFaQ5FHuEq 4feuRqWQAseaZm/4fMphmsyZyxctQFNIs4iWomrhkjgH5mAIKl0KqWVJh1G3nc4MLksU OxlQ== X-Gm-Message-State: APjAAAU4YzhAuhkJJzTLs4w2SEA4xJLSbKXVyvIqXzKx7RtRkst5RUNU B2cU/eIvkq0tot5xIhSlA7S6fV7C X-Google-Smtp-Source: APXvYqzzEJkqP0xxriCFIM3gLN+APTUGH8v+funpGzPT9bHMVlRGQdXem2htbv6FuwCxLX9ZlvrmyQ== X-Received: by 2002:adf:df10:: with SMTP id y16mr11461258wrl.302.1562928638200; Fri, 12 Jul 2019 03:50:38 -0700 (PDT) Received: from localhost ([194.105.145.90]) by smtp.gmail.com with ESMTPSA id c1sm15321378wrh.1.2019.07.12.03.50.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Jul 2019 03:50:37 -0700 (PDT) From: Igor Opaniuk To: u-boot@lists.denx.de Date: Fri, 12 Jul 2019 13:50:31 +0300 Message-Id: <20190712105031.11455-3-igor.opaniuk@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190712105031.11455-1-igor.opaniuk@gmail.com> References: <20190712105031.11455-1-igor.opaniuk@gmail.com> Cc: Igor Opaniuk , Stefan Agner , "NXP i.MX U-Boot Team" Subject: [U-Boot] [PATCH v1 2/2] board: colibri_imx7: reserve DDR memory for Cortex-M4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Igor Opaniuk i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for the rpmsg communication. Both use cases need a fixed location of memory reserved. For the rpmsg use case the reserved area needs to be in sync with the kernel's hardcoded vring descriptor location. Use the linux,usable-memory property to carve out 1MB of memory in case the M4 core is running. Also make sure that the i.MX 7 specific rpmsg driver does not get loaded in case we do not carve out memory. Signed-off-by: Stefan Agner Signed-off-by: Igor Opaniuk Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- arch/arm/include/asm/mach-imx/sys_proto.h | 2 ++ board/toradex/colibri_imx7/colibri_imx7.c | 37 +++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 4925dd7894..775cd3df40 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -113,6 +113,8 @@ void init_src(void); void init_snvs(void); void imx_wdog_disable_powerdown(void); +int arch_auxiliary_core_check_up(u32 core_id); + int board_mmc_get_env_dev(int devno); int nxp_board_rev(void); diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 0eb83474c4..6059088bda 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -333,6 +333,43 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_IMX_BOOTAUX) + int up; + + up = arch_auxiliary_core_check_up(0); + if (up) { + int ret; + int areas = 1; + u64 start[2], size[2]; + + /* + * Reserve 1MB of memory for M4 (1MiB is also the minimum + * alignment for Linux due to MMU section size restrictions). + */ + start[0] = gd->bd->bi_dram[0].start; + size[0] = SZ_256M - SZ_1M; + + /* If needed, create a second entry for memory beyond 256M */ + if (gd->bd->bi_dram[0].size > SZ_256M) { + start[1] = gd->bd->bi_dram[0].start + SZ_256M; + size[1] = gd->bd->bi_dram[0].size - SZ_256M; + areas = 2; + } + + ret = fdt_set_usable_memory(blob, start, size, areas); + if (ret) { + eprintf("Cannot set usable memory\n"); + return ret; + } + } else { + int off; + + off = fdt_node_offset_by_compatible(blob, -1, + "fsl,imx7d-rpmsg"); + if (off > 0) + fdt_status_disabled(blob, off); + } +#endif #if defined(CONFIG_FDT_FIXUP_PARTITIONS) static const struct node_info nodes[] = { { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */