From patchwork Tue Jul 9 14:00:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 1129818 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="B5/7PNe8"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45jkfm3Q4Cz9sBF for ; Wed, 10 Jul 2019 00:07:44 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id DFAD2C21E90; Tue, 9 Jul 2019 14:05:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8AEEFC21E39; Tue, 9 Jul 2019 14:05:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B3137C21EC9; Tue, 9 Jul 2019 14:01:07 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id 06EB9C21C2F for ; Tue, 9 Jul 2019 14:01:03 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id i2so10156616plt.1 for ; Tue, 09 Jul 2019 07:01:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=nLuK1EPS7SbtuVFGWnkgSbTDHTnkobtTHfY/kA/PvGw=; b=B5/7PNe8UtqptHdMXOBEG0QoGWM2RXpz+/72K7bXJsTaCvoLynO5x1pW3Ja46cYAPb OjAFXnNmtr94PyRto25ehsPZWhBX55xg8ca94UL2xIuRQDmrReZ6rW54l2ym0xz8ncuK L1NnmWEKpl4rzZFzaZ6V2sLqwZ4SqHHwZAPkyoMCExXCdIkB9UYcmorctUTrEGGdCmGo lkCKYGqLEDrcgG+JvlD2V+FC4nclC/uHXzxtC7ewdyHN/GdwTMAeglGs80Z/w8Dk34eH hSkjyibTMMa2R0DA+dy5PgN+1D2VAGv7MD0aYx/9fa95CaiaMqiFxGbZGIFO05nGEZTL rNhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=nLuK1EPS7SbtuVFGWnkgSbTDHTnkobtTHfY/kA/PvGw=; b=mb2J0SZAfdd9Gxc4jcQzvLIAji6yyUolAmWf/8OI6W4MapjlFgRb4qggVL88puarsF wnW+5Ui7seuUdwgX8f19vaIKoJ8mRrqJIGSyG8Cehw3GpyKdq0bBV9xYpMXh+nwrymvR tJ2F0xhHFazMaIQI67RkD6xzgxzlbJyWbCkD97d3OKbq0S0YJ4g5wRu4Xt9CPSPd0IRT vmVBPT+/6qFaclNox7opX47LfJd+rl+MLa9OJ+qcHzzJ+I9mNHkzCScZ4OxdgMOvJLCm Ugdl1TJm1+dBLzlnd7vFTeixpPKCUPxRIwY8lYjsKZrsWN9ouffZL7T6Oqszyv0ObH7l pkQw== X-Gm-Message-State: APjAAAWsHydyHdR67aKxWsFzCVE/gLtxO6NdrYLQTY2V/Y3y8oxrkzyb 7Dga8kdcZg2M60yFE5SSlThFLY4a X-Google-Smtp-Source: APXvYqxxbaaYl0fXAJbIgvu9Bk1SvLcS8orAxFs35rp+thwoFkpUtU/6Xliw5/ROCpbCwdsaphJKCg== X-Received: by 2002:a17:902:9b94:: with SMTP id y20mr32437954plp.260.1562680861583; Tue, 09 Jul 2019 07:01:01 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id w1sm2543596pjt.30.2019.07.09.07.00.58 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 09 Jul 2019 07:01:01 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 9 Jul 2019 22:00:23 +0800 Message-Id: <20190709140033.18773-3-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190709140033.18773-1-kever.yang@rock-chips.com> References: <20190709140033.18773-1-kever.yang@rock-chips.com> Cc: Stephen Warren Subject: [U-Boot] [PATCH 02/12] rockchip: rk322x: use ARM arch timer instead of rk_timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track to boot time. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Makefile | 2 +- arch/arm/mach-rockchip/rk322x-board-spl.c | 30 +++++++++++++++++++++ arch/arm/mach-rockchip/rk322x-board-tpl.c | 33 ++++++++++++++++++++--- include/configs/rk322x_common.h | 7 ++--- scripts/config_whitelist.txt | 1 + 5 files changed, 66 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 0c169e9234..933b0a182a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,7 +42,7 @@ endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o ifndef CONFIG_ARM64 -ifndef CONFIG_ROCKCHIP_RK3188 +ifeq ($(CONFIG_ROCKCHIP_RK3188)$(CONFIG_ROCKCHIP_RK322X),) obj-y += rk_timer.o endif endif diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index c9b41c62c0..c825e31c02 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -19,6 +19,31 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; } +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} + #define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) { @@ -31,6 +56,11 @@ void board_init_f(ulong dummy) } preloader_console_init(); + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); + /* Disable the ddr secure region setting to make it non-secure */ rk_clrreg(SGRF_DDR_CON0, 0x4000); } diff --git a/arch/arm/mach-rockchip/rk322x-board-tpl.c b/arch/arm/mach-rockchip/rk322x-board-tpl.c index 92d40ee43a..a0d7bc9b05 100644 --- a/arch/arm/mach-rockchip/rk322x-board-tpl.c +++ b/arch/arm/mach-rockchip/rk322x-board-tpl.c @@ -10,13 +10,37 @@ #include #include #include -#include u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; } +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -39,8 +63,11 @@ void board_init_f(ulong dummy) hang(); } - rockchip_timer_init(); - printf("timer init done\n"); + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { printf("DRAM init failed: %d\n", ret); diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 15bb8d63b8..cc08699944 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -13,9 +13,10 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */ -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020 +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_SYS_INIT_SP_ADDR 0x61100000 #define CONFIG_SYS_LOAD_ADDR 0x61800800 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d252045d80..a69badb5d2 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1540,6 +1540,7 @@ CONFIG_RMSTP9_ENA CONFIG_ROCKCHIP_CHIP_TAG CONFIG_ROCKCHIP_MAX_INIT_SIZE CONFIG_ROCKCHIP_SDHCI_MAX_FREQ +CONFIG_ROCKCHIP_STIMER_BASE CONFIG_ROM_STUBS CONFIG_ROOTFS_OFFSET CONFIG_ROOTPATH