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Mon, 8 Jul 2019 01:39:13 +0000 Received: from AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::2023:c0e5:8a63:2e47]) by AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::2023:c0e5:8a63:2e47%5]) with mapi id 15.20.2052.020; Mon, 8 Jul 2019 01:39:13 +0000 From: Peng Fan To: "sbabic@denx.de" , "festevam@gmail.com" Thread-Topic: [PATCH V2 14/51] imx8m: update imx-regs for i.MX8MM Thread-Index: AQHVNS3ylH/6QRqZV0uu8Yf7+XikEw== Date: Mon, 8 Jul 2019 01:39:13 +0000 Message-ID: <20190708015333.20411-15-peng.fan@nxp.com> References: <20190708015333.20411-1-peng.fan@nxp.com> In-Reply-To: <20190708015333.20411-1-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.16.4 x-clientproxiedby: HK0PR01CA0059.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::23) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.71] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d4a9a1fc-00db-43f1-3f96-08d7034514f4 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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SFP:1101; SCL:1; SRVR:AM0PR04MB5089; H:AM0PR04MB4481.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: mzAB9LFs+g/gjL75697YUhll3hq2VoyRIW/6UzFp5hDlBaNQ8YrXstgKPTV9P5XoHSLs95y6c55C15PpMCU7rTLzrFZOrBJz5dnh+ND8wtfST9coeuHxRxvPx7cOFEW2HNnrGzM9hCcaWXrMmMRuXdO3y5jSM0fzhAGVvCq46RxezmlwXs4AQGZRirsoOB0rssr1p1+LGUh6PDUsDIpd+Ki/GuMqKph9+LpR9Qa8+oqqWr76x7sxtmWLxvzYFZxEhQY8pn/JrYD7dONCSCZLkBXm+UAKBdJ2JiZ+iHEfSLihkGanrU9Gne5W/M8Qh5WoTEpydqeyV89QdjSFeZR3SQKliK+B37b4QctPahtYX9I4lRyF0MoQvI77UqwbdhtvOGMfr42bhfyutubGmc5Zh5MvVPPBUARMMhMgoc3kifE= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d4a9a1fc-00db-43f1-3f96-08d7034514f4 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Jul 2019 01:39:13.6751 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: peng.fan@nxp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5089 Cc: "u-boot@lists.denx.de" , dl-uboot-imx Subject: [U-Boot] [PATCH V2 14/51] imx8m: update imx-regs for i.MX8MM X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" i.MX8MM has similar architecture with i.MX8MQ, but it has totally different PLL design and some register layout change. Note: Some registers in this file are not updated because not used now. Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 75 ++++++++++++++++++++++++++++-- 1 file changed, 71 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 68666a535b..a5be2e85da 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -10,8 +10,8 @@ #include -#define ROM_VERSION_A0 0x800 -#define ROM_VERSION_B0 0x83C +#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800 +#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800 #define M4_BOOTROM_BASE_ADDR 0x007E0000 @@ -93,7 +93,11 @@ #define SEMAPHOR_HS_BASE_ADDR 0x30AC0000 #define USDHC1_BASE_ADDR 0x30B40000 #define USDHC2_BASE_ADDR 0x30B50000 +#ifdef CONFIG_IMX8MM +#define USDHC3_BASE_ADDR 0x30B60000 +#else #define MIPI_CS2_BASE_ADDR 0x30B60000 +#endif #define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000 #define CSI2_BASE_ADDR 0x30B80000 #define QSPI0_BASE_ADDR 0x30BB0000 @@ -120,7 +124,8 @@ #define USB1_PHY_BASE_ADDR 0x381F0000 #define USB2_PHY_BASE_ADDR 0x382F0000 -#define MXS_LCDIF_BASE LCDIF_BASE_ADDR +#define MXS_LCDIF_BASE is_enable(CONFIG_IMX8MQ) ? \ + 0x30320000 : 0x32e00000 #define SRC_IPS_BASE_ADDR 0x30390000 #define SRC_DDRC_RCR_ADDR 0x30391000 @@ -149,6 +154,9 @@ #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 + struct iomuxc_gpr_base_regs { u32 gpr[47]; }; @@ -205,6 +213,7 @@ struct fuse_bank1_regs { u32 rsvd3[3]; }; +#ifdef CONFIG_IMX8MQ struct anamix_pll { u32 audio_pll1_cfg0; u32 audio_pll1_cfg1; @@ -239,6 +248,60 @@ struct anamix_pll { u32 frac_pllout_div_cfg; u32 sscg_pllout_div_cfg; }; +#else +struct anamix_pll { + u32 audio_pll1_gnrl_ctl; + u32 audio_pll1_fdiv_ctl0; + u32 audio_pll1_fdiv_ctl1; + u32 audio_pll1_sscg_ctl; + u32 audio_pll1_mnit_ctl; + u32 audio_pll2_gnrl_ctl; + u32 audio_pll2_fdiv_ctl0; + u32 audio_pll2_fdiv_ctl1; + u32 audio_pll2_sscg_ctl; + u32 audio_pll2_mnit_ctl; + u32 video_pll1_gnrl_ctl; + u32 video_pll1_fdiv_ctl0; + u32 video_pll1_fdiv_ctl1; + u32 video_pll1_sscg_ctl; + u32 video_pll1_mnit_ctl; + u32 reserved[5]; + u32 dram_pll_gnrl_ctl; + u32 dram_pll_fdiv_ctl0; + u32 dram_pll_fdiv_ctl1; + u32 dram_pll_sscg_ctl; + u32 dram_pll_mnit_ctl; + u32 gpu_pll_gnrl_ctl; + u32 gpu_pll_div_ctl; + u32 gpu_pll_locked_ctl1; + u32 gpu_pll_mnit_ctl; + u32 vpu_pll_gnrl_ctl; + u32 vpu_pll_div_ctl; + u32 vpu_pll_locked_ctl1; + u32 vpu_pll_mnit_ctl; + u32 arm_pll_gnrl_ctl; + u32 arm_pll_div_ctl; + u32 arm_pll_locked_ctl1; + u32 arm_pll_mnit_ctl; + u32 sys_pll1_gnrl_ctl; + u32 sys_pll1_div_ctl; + u32 sys_pll1_locked_ctl1; + u32 reserved2[24]; + u32 sys_pll1_mnit_ctl; + u32 sys_pll2_gnrl_ctl; + u32 sys_pll2_div_ctl; + u32 sys_pll2_locked_ctl1; + u32 sys_pll2_mnit_ctl; + u32 sys_pll3_gnrl_ctl; + u32 sys_pll3_div_ctl; + u32 sys_pll3_locked_ctl1; + u32 sys_pll3_mnit_ctl; + u32 anamix_misc_ctl; + u32 anamix_clk_mnit_ctl; + u32 reserved3[437]; + u32 digprog; +}; +#endif struct fuse_bank9_regs { u32 mac_addr0; @@ -258,11 +321,13 @@ struct src { u32 usbophy2_rcr; u32 mipiphy_rcr; u32 pciephy_rcr; + /* Exits on i.MX8MQ */ u32 hdmi_rcr; u32 disp_rcr; u32 reserved2[2]; u32 gpu_rcr; u32 vpu_rcr; + /* The following four exits on i.MX8MQ */ u32 pcie2_rcr; u32 mipiphy1_rcr; u32 mipiphy2_rcr; @@ -285,6 +350,7 @@ struct src { u32 gpr10; u32 reserved5[985]; u32 ddr1_rcr; + /* Exist on i.MX8MQ */ u32 ddr2_rcr; }; @@ -459,7 +525,8 @@ struct bootrom_sw_info { u32 reserved_3[3]; }; -#define ROM_SW_INFO_ADDR_B0 0x00000968 +#define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\ + 0x000009e8) #define ROM_SW_INFO_ADDR_A0 0x000009e8 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \