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Thu, 20 Jun 2019 06:48:56 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::84da:b4e7:4612:48b]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::84da:b4e7:4612:48b%7]) with mapi id 15.20.1987.014; Thu, 20 Jun 2019 06:48:56 +0000 From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer , Simon Glass Thread-Topic: [PATCH v5 3/8] clk: sifive: Sync-up DT bindings header with upstream Linux Thread-Index: AQHVJzQ7TV9ZRMm9A0mT6qs4vHL0mQ== Date: Thu, 20 Jun 2019 06:48:56 +0000 Message-ID: <20190620064753.32391-4-anup.patel@wdc.com> References: <20190620064753.32391-1-anup.patel@wdc.com> In-Reply-To: <20190620064753.32391-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: TY1PR01CA0181.jpnprd01.prod.outlook.com (2603:1096:402::33) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [129.253.179.161] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 7e1f8cd5-47e0-420d-16a6-08d6f54b5d6a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB5966; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: u4DQFmdsKu6EViBXKuy5hHzMitB9sHL8dRw4mr4EFdtVpfCQbwxd7fUd1lqVz6P5HX+GyIw4g03WuzH/XDlDBiwBPTMHB5edMtQAS8DpO334bDL2JJh0Bse5t4LeuXmKgKmMRNxTz444fvzIU7loX5lk7ybt8tP6ASJ2+GaZqNbkgU0wLhqzvRXnFBKsn9D+mHfpVk5SxhHmpci7RJJnjDQMJZRIOfqZDlwEDQ4mCrxZ91JrzDv4eg/AluRbTHBpkw2KjYhsNqxhBLIsPOFhj8lzu4QaDiqo8PG3wcthLtRBTd63AxhpTW3MfGXr0T8aNoZXM+850SjkRkpn+kVWwQiJGZ9BzvNuw1Q9hKogJYgB6usm6uPUQUfaSl+tFscTutk8aGcu4EfkfT9setdEF4G76ACI9+KH6dmOUY+JjaU= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7e1f8cd5-47e0-420d-16a6-08d6f54b5d6a X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Jun 2019 06:48:56.1658 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Anup.Patel@wdc.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5966 Cc: U-Boot Mailing List , Palmer Dabbelt , Joe Hershberger , Alistair Francis Subject: [U-Boot] [PATCH v5 3/8] clk: sifive: Sync-up DT bindings header with upstream Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The location and license header of DT bindings header for SiFive clock driver has changed in upstream Linux hence this patch. Signed-off-by: Anup Patel --- drivers/clk/sifive/fu540-prci.c | 2 +- include/dt-bindings/clk/sifive-fu540-prci.h | 29 ------------------- include/dt-bindings/clock/sifive-fu540-prci.h | 18 ++++++++++++ 3 files changed, 19 insertions(+), 30 deletions(-) delete mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h create mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index cdbf35e871..ceb318e062 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -38,7 +38,7 @@ #include #include -#include +#include /* * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: diff --git a/include/dt-bindings/clk/sifive-fu540-prci.h b/include/dt-bindings/clk/sifive-fu540-prci.h deleted file mode 100644 index 531523ea62..0000000000 --- a/include/dt-bindings/clk/sifive-fu540-prci.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 Western Digital Corporation or its affiliates. - * - * Copyright (C) 2018 SiFive, Inc. - * Wesley Terpstra - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __LINUX_CLK_SIFIVE_FU540_PRCI_H -#define __LINUX_CLK_SIFIVE_FU540_PRCI_H - -/* Clock indexes for use by Device Tree data */ - -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 - -#endif diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h new file mode 100644 index 0000000000..6a0b70a37d --- /dev/null +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018-2019 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + */ + +#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H + +/* Clock indexes for use by Device Tree data and the PRCI driver */ + +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + +#endif