From patchwork Mon Jun 17 07:32:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1116801 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="LUX5HCfC"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45S3m044gBz9s3C for ; Mon, 17 Jun 2019 18:09:52 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 30CBAC21E44; Mon, 17 Jun 2019 07:49:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 783B6C21F42; Mon, 17 Jun 2019 07:42:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3C704C21DF8; Mon, 17 Jun 2019 07:40:30 +0000 (UTC) Received: from mail-pf1-f193.google.com (mail-pf1-f193.google.com [209.85.210.193]) by lists.denx.de (Postfix) with ESMTPS id A9ECEC21E1D for ; Mon, 17 Jun 2019 07:40:24 +0000 (UTC) Received: by mail-pf1-f193.google.com with SMTP id i189so5185000pfg.10 for ; Mon, 17 Jun 2019 00:40:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t8d2qnZ3kav7gpkrZS6dlrZ+F/FMvW3L+8hK+xgO7jQ=; b=LUX5HCfCqKsiKUg+7MDKKQsXg3fyx99MlPuCpVzeLNyaGuS2hJ8JApE7wOrkZFniss uUjyCc1IViyDWhPA3pA3KSxV2E0C2zV2vfkQn3oxZQYvNLbIn/LEVzqnIjHop7Udo13f pERZdBku09uPAnjaSnN+NL0PPzWWCMOcL/c+c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t8d2qnZ3kav7gpkrZS6dlrZ+F/FMvW3L+8hK+xgO7jQ=; b=l3WbtrEkG5PKra1gqXTZJKJ9YcguDVZOwOIWzgUSL9arVdSGkz5+YgcYX9SlueIiCF m35d/VXl88g/ZWUeOy98qAk+sI7/YV6NA/QyN2LKdcfQI+Rgno3ARtSDJ8GfKrhXZlDK hgkskHuLeA0HmmUqtHGrF8VbjkofNrYSkJGUQqDDsseJLrysf6MH2h6AQvm/rwHCBJWk BgcEWU5s4j8LRYXYUzz1P3Ltb8WXI0Pf+L9R305ah3wz+1BxnGXRAyTGW9Shbv98wyYb iS6+GEiRGyeTxpLXfpPJDm5cQrnn7OB726Pa51l2A6kmWJqp3w/XOeqZAj2P+5Kf/VEb NyqQ== X-Gm-Message-State: APjAAAWXno1yrYQcm12a/GfgQ74AC8opv1RRcBQXtnNxS45KsBv/psGZ //H9sTcKv5JIJMq+kdy2MOaBWg== X-Google-Smtp-Source: APXvYqxQEXDM7w8E1LFjL1GZkHbOJbGJ3UuB1mdpykWL4V6O6ntbQev+2SyFt7NMEvaZGmxnZ6xC/Q== X-Received: by 2002:a17:90a:ab0b:: with SMTP id m11mr3432830pjq.73.1560757223299; Mon, 17 Jun 2019 00:40:23 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.245]) by smtp.gmail.com with ESMTPSA id m41sm15205998pje.18.2019.06.17.00.40.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 00:40:22 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Date: Mon, 17 Jun 2019 13:02:26 +0530 Message-Id: <20190617073252.27810-74-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190617073252.27810-1-jagan@amarulasolutions.com> References: <20190617073252.27810-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Manivannan Sadhasivam Subject: [U-Boot] [PATCH v2 73/99] ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Now we have IO settings available for all supported sdram frequencies, so retrieve these IO settings and make used for LPDDR4 ds odt configuration. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 42 ++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 4de5a208f5..22c1a66185 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -184,6 +184,33 @@ struct io_setting { }, }; +/** + * phy = 0, PHY boot freq + * phy = 1, PHY index 0 + * phy = 2, PHY index 1 + */ +static struct io_setting * +lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5) +{ + struct io_setting *io = NULL; + u32 n; + + for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) { + io = &lpddr4_io_setting[n]; + + if (io->mr5 != 0) { + if (io->mhz >= params->base.ddr_freq && + io->mr5 == mr5) + break; + } else { + if (io->mhz >= params->base.ddr_freq) + break; + } + } + + return io; +} + static void *get_ddrc0_con(struct dram_info *dram, u8 channel) { return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1; @@ -524,7 +551,7 @@ static int phy_io_config(const struct chan_info *chan, } static void set_ds_odt(const struct chan_info *chan, - const struct rk3399_sdram_params *params) + const struct rk3399_sdram_params *params, u32 mr5) { u32 *denali_phy = chan->publ->denali_phy; @@ -533,19 +560,22 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_select_n, tsel_rd_select_n; u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; + struct io_setting *io = NULL; u32 reg_value; if (params->base.dramtype == LPDDR4) { + io = lpddr4_get_io_settings(params, mr5); + tsel_rd_select_p = PHY_DRV_ODT_HI_Z; - tsel_rd_select_n = PHY_DRV_ODT_240; + tsel_rd_select_n = io->rd_odt; tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_idle_select_n = PHY_DRV_ODT_240; - tsel_wr_select_dq_p = PHY_DRV_ODT_40; + tsel_wr_select_dq_p = io->wr_dq_drv; tsel_wr_select_dq_n = PHY_DRV_ODT_40; - tsel_wr_select_ca_p = PHY_DRV_ODT_40; + tsel_wr_select_ca_p = io->wr_ca_drv; tsel_wr_select_ca_n = PHY_DRV_ODT_40; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -723,7 +753,7 @@ static void pctl_start(struct dram_info *dram, u8 channel) } static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, - u32 channel, const struct rk3399_sdram_params *params) + u32 channel, struct rk3399_sdram_params *params) { u32 *denali_ctl = chan->pctl->denali_ctl; u32 *denali_pi = chan->pi->denali_pi; @@ -805,7 +835,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); - set_ds_odt(chan, params); + set_ds_odt(chan, params, 0); /* * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8