From patchwork Fri May 31 16:00:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1108425 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45Fq2P60vFz9s3l for ; Sat, 1 Jun 2019 02:01:49 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 69661C21D8A; Fri, 31 May 2019 16:00:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4D55CC21CB1; Fri, 31 May 2019 16:00:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A8A4EC21D8E; Fri, 31 May 2019 16:00:49 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lists.denx.de (Postfix) with ESMTPS id ABB6BC21D8E for ; Fri, 31 May 2019 16:00:45 +0000 (UTC) Received: from marcel-nb-toradex-int.toradex.int ([194.105.145.87]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1N8Won-1gSaXf3eQT-014S68; Fri, 31 May 2019 18:00:39 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Fri, 31 May 2019 19:00:17 +0300 Message-Id: <20190531160020.9755-4-marcel@ziswiler.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190531160020.9755-1-marcel@ziswiler.com> References: <20190531160020.9755-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:eYFK6HOc0ZCENAI30i2tZbqt5At7Hm8eCxOUnpWfawxKTw5ES2K WiEx3V1hxAot/G8WT8neJ95xtbzY+5gCUQomfcn4oRLjpelpjKVknXa4EXmDgoyA6YF2leb zc3AXS0wRpYLpzKcSdaXHDdfrDMmlJP/9RP9lKedPKUjIkXqAmGN4H7PrUr+ajOObjB6tHj hH3epiSie7Z30oyj1PYgg== X-UI-Out-Filterresults: notjunk:1; V03:K0:2pcmDqVtZ0g=:RYxV+PeQLdi54CA6gs+Co9 MWU0Bx+FPK/zIyuBDKWqM8vm+ZF4Zwb9m0AkLN8N03Rl0PTqfN3AIQ0gSGXr6zerGh51qAJzx LccLeY+EkHpCSumRlfyoWbwc39oeZrg4zbDWYvjtBr9hphQbZcflXyMNT+RyXJluVMXL89bzy 23NE0aEB4SBA8t5nS1t8hGqAXtIgF1oV2thU6TLFe4keN3imu29AmD1oG6Kf4qaNY1foVmwNW U2/KOMGgn1uafYpdxnF/kfTCgJb6XgdKaC7VppwzfWuzgtHtAJoEmJKbALLwFMgBANl0j7lIb onyNgudEWuRi5/GX5OJ5rgm7W1qUi9IurobuoRLybjqMBOCEmSPhk1/cu3Nqw3Eg8g+QzhQi8 X8mHkMwSEopJ2gp+XwtvJFp1GgbZ9Cb72lBw9KjCC4hs4Zc4Dcsz8YG0gjnNBHWqyowCeFEW5 d9sCOyeLjjqzOJBwVO0ihaBBrPANWzB8sxF0+pIMyC7sIZZ7x49NKqlwy0VM417e/dl94Ill4 pis3PcYDquE8/rSWrqMl+k0GghChlkHcjOtXJv868s2i2SyPE5atFOr+DApDtBHUJ0QjTT1U+ GaUkzxH2+Egbd/TiBYk94nVkcX/9FnYDJZ3hAMO/528uMwnuRPXHcmPPIqdQ1UEAXoJ26lWVu Y3cPOwZZ0RBrEQKnHGUQDkHz2h6yVKhgtc7a/4eq9aPe6fVwfbQ6XUBTSpBjkDXKd41+siEjd HpTADUI3rbveLoX0OHo5NuMrMWyTdUe2teRdSg== Cc: Tom Rini , Marcel Ziswiler , Marcel Ziswiler , Max Krummenacher , Fabio Estevam Subject: [U-Boot] [PATCH v3 3/6] clk: imx8qm: fix usdhc2 clocks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Trying to bring up uSDHC2 the following error message was observed: MMC: imx8_clk_set_rate(Invalid clk ID #60) imx8_clk_set_rate(Invalid clk ID #60) usdhc@5b030000 - probe failed: -22 This commit fixes this by properly setting resp. clocks. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- Changes in v3: None Changes in v2: None drivers/clk/imx/clk-imx8qm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 6b5561e178..a6b09d2109 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -80,6 +80,12 @@ ulong imx8_clk_get_rate(struct clk *clk) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_UART0_IPG_CLK: case IMX8QM_UART0_CLK: resource = SC_R_UART_0; @@ -185,6 +191,12 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_ENET0_IPG_CLK: case IMX8QM_ENET0_AHB_CLK: case IMX8QM_ENET0_REF_DIV: @@ -273,6 +285,12 @@ int __imx8_clk_enable(struct clk *clk, bool enable) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_ENET0_IPG_CLK: case IMX8QM_ENET0_AHB_CLK: case IMX8QM_ENET0_REF_DIV: