diff mbox series

[U-Boot,PATCHv2,1/2] PCI: layerscape: Add Support for ls2088 PCIeEP mode

Message ID 20190516110408.45169-1-xiaowei.bao@nxp.com
State Changes Requested
Delegated to: Prabhakar Kushwaha
Headers show
Series [U-Boot,PATCHv2,1/2] PCI: layerscape: Add Support for ls2088 PCIeEP mode | expand

Commit Message

Xiaowei Bao May 16, 2019, 11:02 a.m. UTC 
From: Xiaowei Bao <xiaowei.bao@nxp.com>

Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2:
 - Add the NXP copyright and make the function readability.

 drivers/pci/pcie_layerscape.c |  117 +++++++++++++++++++++++++++--------------
 drivers/pci/pcie_layerscape.h |   19 +++++--
 2 files changed, 91 insertions(+), 45 deletions(-)

Comments

Bin Meng May 16, 2019, 11:57 a.m. UTC | #1 
Hi,

On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
>
> Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> ---
> v2:
>  - Add the NXP copyright and make the function readability.
>
>  drivers/pci/pcie_layerscape.c |  117 +++++++++++++++++++++++++++--------------
>  drivers/pci/pcie_layerscape.h |   19 +++++--
>  2 files changed, 91 insertions(+), 45 deletions(-)
>

Could you please support the PCIe EP mode using driver model?

Regards,
Bin
Xiaowei Bao May 17, 2019, 2:23 a.m. UTC | #2 
-----Original Message-----
From: Bin Meng <bmeng.cn@gmail.com> 
Sent: 2019年5月16日 19:58
To: Xiaowei Bao <xiaowei.bao@nxp.com>
Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>; u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode

Caution: EXT Email

Hi,

On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
>
> Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> ---
> v2:
>  - Add the NXP copyright and make the function readability.
>
>  drivers/pci/pcie_layerscape.c |  117 +++++++++++++++++++++++++++--------------
>  drivers/pci/pcie_layerscape.h |   19 +++++--
>  2 files changed, 91 insertions(+), 45 deletions(-)
>

Could you please support the PCIe EP mode using driver model?
[Xiaowei Bao] do you mean that add a EP driver model to separate the RC and EP with their respective drivers? 
The purpose of adding EP support under u-boot is to configure the size of the BAR when the PCIE controller is used as an EP device, and to ensure that the configuration space of the EP can be accessed, so that when the RC scans the bus, the EP device can be scanned, and we also can do simple MEM read and write verification through the md command in u-boot shell. 
When entering the kernel, the kernel has its own PCIE EP framework, which will reinitialize the EP device, contain of the inbound and outbound window configure, MSI configuration and so no.

Regards,
Bin
Bin Meng May 17, 2019, 2:31 a.m. UTC | #3 
Hi Xiaowei,

On Fri, May 17, 2019 at 10:23 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
>
>
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年5月16日 19:58
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>; u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode
>
> Caution: EXT Email
>
> Hi,
>
> On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> >
> > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> >
> > Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > ---
> > v2:
> >  - Add the NXP copyright and make the function readability.
> >
> >  drivers/pci/pcie_layerscape.c |  117 +++++++++++++++++++++++++++--------------
> >  drivers/pci/pcie_layerscape.h |   19 +++++--
> >  2 files changed, 91 insertions(+), 45 deletions(-)
> >
>
> Could you please support the PCIe EP mode using driver model?
> [Xiaowei Bao] do you mean that add a EP driver model to separate the RC and EP with their respective drivers?

That's correct.

> The purpose of adding EP support under u-boot is to configure the size of the BAR when the PCIE controller is used as an EP device, and to ensure that the configuration space of the EP can be accessed, so that when the RC scans the bus, the EP device can be scanned, and we also can do simple MEM read and write verification through the md command in u-boot shell.
> When entering the kernel, the kernel has its own PCIE EP framework, which will reinitialize the EP device, contain of the inbound and outbound window configure, MSI configuration and so no.
>

It's not kernel PCIe EP framework. Ramon Fried recently added PCIe EP
uclass support to U-Boot and you should add NXP layerscape PCIe EP
driver using the new EP uclass.

See http://patchwork.ozlabs.org/project/uboot/list/?series=104952

Regards,
Bin
Xiaowei Bao May 22, 2019, 10:19 a.m. UTC | #4 
Hi Bin,

-----Original Message-----
From: Bin Meng <bmeng.cn@gmail.com> 
Sent: 2019年5月17日 10:31
To: Xiaowei Bao <xiaowei.bao@nxp.com>; Ramon Fried <ramon.fried@gmail.com>; Simon Glass <sjg@chromium.org>
Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>; u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode

Caution: EXT Email

Hi Xiaowei,

On Fri, May 17, 2019 at 10:23 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
>
>
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年5月16日 19:58
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou 
> <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang 
> <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>; 
> u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support 
> for ls2088 PCIe EP mode
>
> Caution: EXT Email
>
> Hi,
>
> On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> >
> > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> >
> > Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > ---
> > v2:
> >  - Add the NXP copyright and make the function readability.
> >
> >  drivers/pci/pcie_layerscape.c |  117 +++++++++++++++++++++++++++--------------
> >  drivers/pci/pcie_layerscape.h |   19 +++++--
> >  2 files changed, 91 insertions(+), 45 deletions(-)
> >
>
> Could you please support the PCIe EP mode using driver model?
> [Xiaowei Bao] do you mean that add a EP driver model to separate the RC and EP with their respective drivers?

That's correct.

> The purpose of adding EP support under u-boot is to configure the size of the BAR when the PCIE controller is used as an EP device, and to ensure that the configuration space of the EP can be accessed, so that when the RC scans the bus, the EP device can be scanned, and we also can do simple MEM read and write verification through the md command in u-boot shell.
> When entering the kernel, the kernel has its own PCIE EP framework, which will reinitialize the EP device, contain of the inbound and outbound window configure, MSI configuration and so no.
>

It's not kernel PCIe EP framework. Ramon Fried recently added PCIe EP uclass support to U-Boot and you should add NXP layerscape PCIe EP driver using the new EP uclass.
[Xiaowei Bao] OK, thanks, I will add NXP layerscape PCIe EP driver using the new EP uclass.

See https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D104952&amp;data=02%7C01%7Cxiaowei.bao%40nxp.com%7Ca1e3da7d57a54520bd3008d6da6fbc4d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C636936570769296107&amp;sdata=5CnEujEtYGbeiBEyv4iY5dXAapdQ65wCh1vs0quSVTY%3D&amp;reserved=0

Regards,
Bin
Xiaowei Bao Nov. 19, 2019, 3:27 a.m. UTC | #5 
> -----Original Message-----
> From: Xiaowei Bao
> Sent: 2019年5月22日 18:19
> To: Bin Meng <bmeng.cn@gmail.com>; Ramon Fried
> <ramon.fried@gmail.com>; Simon Glass <sjg@chromium.org>
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang
> <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support
> for ls2088 PCIe EP mode
> 
> Hi Bin,
> 
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年5月17日 10:31
> To: Xiaowei Bao <xiaowei.bao@nxp.com>; Ramon Fried
> <ramon.fried@gmail.com>; Simon Glass <sjg@chromium.org>
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang
> <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support
> for ls2088 PCIe EP mode
> 
> Caution: EXT Email
> 
> Hi Xiaowei,
> 
> On Fri, May 17, 2019 at 10:23 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> wrote:
> >
> >
> >
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 2019年5月16日 19:58
> > To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou
> > <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo
> Wang
> > <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> > u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> > Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support
> > for ls2088 PCIe EP mode
> >
> > Caution: EXT Email
> >
> > Hi,
> >
> > On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao <xiaowei.bao@nxp.com>
> wrote:
> > >
> > > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> > >
> > > Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
> > > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > ---
> > > v2:
> > >  - Add the NXP copyright and make the function readability.
> > >
> > >  drivers/pci/pcie_layerscape.c |  117
> +++++++++++++++++++++++++++--------------
> > >  drivers/pci/pcie_layerscape.h |   19 +++++--
> > >  2 files changed, 91 insertions(+), 45 deletions(-)
> > >
> >
> > Could you please support the PCIe EP mode using driver model?
> > [Xiaowei Bao] do you mean that add a EP driver model to separate the RC
> and EP with their respective drivers?
> 
> That's correct.
> 
> > The purpose of adding EP support under u-boot is to configure the size of the
> BAR when the PCIE controller is used as an EP device, and to ensure that the
> configuration space of the EP can be accessed, so that when the RC scans the
> bus, the EP device can be scanned, and we also can do simple MEM read and
> write verification through the md command in u-boot shell.
> > When entering the kernel, the kernel has its own PCIE EP framework, which
> will reinitialize the EP device, contain of the inbound and outbound window
> configure, MSI configuration and so no.
> >
> 
> It's not kernel PCIe EP framework. Ramon Fried recently added PCIe EP uclass
> support to U-Boot and you should add NXP layerscape PCIe EP driver using the
> new EP uclass.
> [Xiaowei Bao] OK, thanks, I will add NXP layerscape PCIe EP driver using the
> new EP uclass.

Hi Bin and Ramon,

Do you know how to test the EP device when use Ramon Fried EP framework patch,
I don't know how to use it in u-boot, take our board as an example, we use the RCW to 
configure the PCIe controller work as EP or RC, never use the DTS, another issue, when 
our PCIe controller work in EP mode, we must set this controller is ready before RC scan 
the bus, our main purpose is that set the BAR size and make it ready in u-boot, ensure that
the EP controller is ready when enter the kernel or other RC can scan the bus which the EP link,
I am not sure whether should separate the EP and RC driver. Do you have any advice?  

Thanks
Xiaowei

> 
> See
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchw
> ork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D104952&amp;da
> ta=02%7C01%7Cxiaowei.bao%40nxp.com%7Ca1e3da7d57a54520bd3008d6d
> a6fbc4d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C63693657
> 0769296107&amp;sdata=5CnEujEtYGbeiBEyv4iY5dXAapdQ65wCh1vs0quSVT
> Y%3D&amp;reserved=0
> 
> Regards,
> Bin
Ramon Fried Nov. 19, 2019, 6:50 p.m. UTC | #6 
On Tue, Nov 19, 2019 at 5:27 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Xiaowei Bao
> > Sent: 2019年5月22日 18:19
> > To: Bin Meng <bmeng.cn@gmail.com>; Ramon Fried
> > <ramon.fried@gmail.com>; Simon Glass <sjg@chromium.org>
> > Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>;
> > Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang
> > <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> > u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> > Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support
> > for ls2088 PCIe EP mode
> >
> > Hi Bin,
> >
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 2019年5月17日 10:31
> > To: Xiaowei Bao <xiaowei.bao@nxp.com>; Ramon Fried
> > <ramon.fried@gmail.com>; Simon Glass <sjg@chromium.org>
> > Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>;
> > Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang
> > <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> > u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> > Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support
> > for ls2088 PCIe EP mode
> >
> > Caution: EXT Email
> >
> > Hi Xiaowei,
> >
> > On Fri, May 17, 2019 at 10:23 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> > wrote:
> > >
> > >
> > >
> > > -----Original Message-----
> > > From: Bin Meng <bmeng.cn@gmail.com>
> > > Sent: 2019年5月16日 19:58
> > > To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou
> > > <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo
> > Wang
> > > <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> > > u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> > > Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support
> > > for ls2088 PCIe EP mode
> > >
> > > Caution: EXT Email
> > >
> > > Hi,
> > >
> > > On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao <xiaowei.bao@nxp.com>
> > wrote:
> > > >
> > > > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > >
> > > > Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
> > > > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > ---
> > > > v2:
> > > >  - Add the NXP copyright and make the function readability.
> > > >
> > > >  drivers/pci/pcie_layerscape.c |  117
> > +++++++++++++++++++++++++++--------------
> > > >  drivers/pci/pcie_layerscape.h |   19 +++++--
> > > >  2 files changed, 91 insertions(+), 45 deletions(-)
> > > >
> > >
> > > Could you please support the PCIe EP mode using driver model?
> > > [Xiaowei Bao] do you mean that add a EP driver model to separate the RC
> > and EP with their respective drivers?
> >
> > That's correct.
> >
> > > The purpose of adding EP support under u-boot is to configure the size of the
> > BAR when the PCIE controller is used as an EP device, and to ensure that the
> > configuration space of the EP can be accessed, so that when the RC scans the
> > bus, the EP device can be scanned, and we also can do simple MEM read and
> > write verification through the md command in u-boot shell.
> > > When entering the kernel, the kernel has its own PCIE EP framework, which
> > will reinitialize the EP device, contain of the inbound and outbound window
> > configure, MSI configuration and so no.
> > >
> >
> > It's not kernel PCIe EP framework. Ramon Fried recently added PCIe EP uclass
> > support to U-Boot and you should add NXP layerscape PCIe EP driver using the
> > new EP uclass.
> > [Xiaowei Bao] OK, thanks, I will add NXP layerscape PCIe EP driver using the
> > new EP uclass.
>
> Hi Bin and Ramon,
>
> Do you know how to test the EP device when use Ramon Fried EP framework patch,
> I don't know how to use it in u-boot, take our board as an example, we use the RCW to
> configure the PCIe controller work as EP or RC, never use the DTS, another issue, when
> our PCIe controller work in EP mode, we must set this controller is ready before RC scan
> the bus, our main purpose is that set the BAR size and make it ready in u-boot, ensure that
> the EP controller is ready when enter the kernel or other RC can scan the bus which the EP link,
> I am not sure whether should separate the EP and RC driver. Do you have any advice?
>
In this case, where you need to initialize the EP as fast as possible,
you should define the dts node and probably add ""u-boot,
dm-pre-reloc".
The you need to forcefully probe the EP in one of the pre-relocation
board callbacks.
This can be done by something like:
rc = uclass_get_device_by_name(UCLASS_PCI_EP, "pcie_ep@4800000", &dev);

root complex and endpoint are totally different drivers, I don't see
how you can combine them together.

Thanks,
Ramon.


> Thanks
> Xiaowei
>
> >
> > See
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchw
> > ork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D104952&amp;da
> > ta=02%7C01%7Cxiaowei.bao%40nxp.com%7Ca1e3da7d57a54520bd3008d6d
> > a6fbc4d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C63693657
> > 0769296107&amp;sdata=5CnEujEtYGbeiBEyv4iY5dXAapdQ65wCh1vs0quSVT
> > Y%3D&amp;reserved=0
> >
> > Regards,
> > Bin
Xiaowei Bao Nov. 20, 2019, 3:27 a.m. UTC | #7 
> -----Original Message-----
> From: Ramon Fried <ramon.fried@gmail.com>
> Sent: 2019年11月20日 2:50
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>;
> M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang
> <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> u-boot@lists.denx.de
> Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support
> for ls2088 PCIe EP mode
> 
> On Tue, Nov 19, 2019 at 5:27 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Xiaowei Bao
> > > Sent: 2019年5月22日 18:19
> > > To: Bin Meng <bmeng.cn@gmail.com>; Ramon Fried
> > > <ramon.fried@gmail.com>; Simon Glass <sjg@chromium.org>
> > > Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou
> > > <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo
> Wang
> > > <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> > > u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> > > Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > > Support for ls2088 PCIe EP mode
> > >
> > > Hi Bin,
> > >
> > > -----Original Message-----
> > > From: Bin Meng <bmeng.cn@gmail.com>
> > > Sent: 2019年5月17日 10:31
> > > To: Xiaowei Bao <xiaowei.bao@nxp.com>; Ramon Fried
> > > <ramon.fried@gmail.com>; Simon Glass <sjg@chromium.org>
> > > Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou
> > > <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo
> Wang
> > > <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> > > u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> > > Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > > Support for ls2088 PCIe EP mode
> > >
> > > Caution: EXT Email
> > >
> > > Hi Xiaowei,
> > >
> > > On Fri, May 17, 2019 at 10:23 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> > > wrote:
> > > >
> > > >
> > > >
> > > > -----Original Message-----
> > > > From: Bin Meng <bmeng.cn@gmail.com>
> > > > Sent: 2019年5月16日 19:58
> > > > To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou
> > > > <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo
> > > Wang
> > > > <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> > > > u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> > > > Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > > > Support for ls2088 PCIe EP mode
> > > >
> > > > Caution: EXT Email
> > > >
> > > > Hi,
> > > >
> > > > On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao <xiaowei.bao@nxp.com>
> > > wrote:
> > > > >
> > > > > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > >
> > > > > Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
> > > > > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > > ---
> > > > > v2:
> > > > >  - Add the NXP copyright and make the function readability.
> > > > >
> > > > >  drivers/pci/pcie_layerscape.c |  117
> > > +++++++++++++++++++++++++++--------------
> > > > >  drivers/pci/pcie_layerscape.h |   19 +++++--
> > > > >  2 files changed, 91 insertions(+), 45 deletions(-)
> > > > >
> > > >
> > > > Could you please support the PCIe EP mode using driver model?
> > > > [Xiaowei Bao] do you mean that add a EP driver model to separate
> > > > the RC
> > > and EP with their respective drivers?
> > >
> > > That's correct.
> > >
> > > > The purpose of adding EP support under u-boot is to configure the
> > > > size of the
> > > BAR when the PCIE controller is used as an EP device, and to ensure
> > > that the configuration space of the EP can be accessed, so that when
> > > the RC scans the bus, the EP device can be scanned, and we also can
> > > do simple MEM read and write verification through the md command in
> u-boot shell.
> > > > When entering the kernel, the kernel has its own PCIE EP
> > > > framework, which
> > > will reinitialize the EP device, contain of the inbound and outbound
> > > window configure, MSI configuration and so no.
> > > >
> > >
> > > It's not kernel PCIe EP framework. Ramon Fried recently added PCIe
> > > EP uclass support to U-Boot and you should add NXP layerscape PCIe
> > > EP driver using the new EP uclass.
> > > [Xiaowei Bao] OK, thanks, I will add NXP layerscape PCIe EP driver
> > > using the new EP uclass.
> >
> > Hi Bin and Ramon,
> >
> > Do you know how to test the EP device when use Ramon Fried EP
> > framework patch, I don't know how to use it in u-boot, take our board
> > as an example, we use the RCW to configure the PCIe controller work as
> > EP or RC, never use the DTS, another issue, when our PCIe controller
> > work in EP mode, we must set this controller is ready before RC scan
> > the bus, our main purpose is that set the BAR size and make it ready
> > in u-boot, ensure that the EP controller is ready when enter the kernel or
> other RC can scan the bus which the EP link, I am not sure whether should
> separate the EP and RC driver. Do you have any advice?
> >
> In this case, where you need to initialize the EP as fast as possible, you should
> define the dts node and probably add ""u-boot, dm-pre-reloc".
> The you need to forcefully probe the EP in one of the pre-relocation board
> callbacks.
> This can be done by something like:
> rc = uclass_get_device_by_name(UCLASS_PCI_EP, "pcie_ep@4800000",
> &dev);:q

Thanks a lot, could you tell me when call the uclass_get_device_by_name function?

Actually, I am not very clear how to run the DM_TEST in test/dm/pci_ep.c
maybe I need to learn more DM and UCLASS knowledge, if you can explain it, I will be
very appreciate. 

> 
> root complex and endpoint are totally different drivers, I don't see how you
> can combine them together.

Thanks a lot form your comments, we combine the RC and EP driver in one
file(drivers/pci/pcie_layerscape.c), and we run the different initialize code of EP
and RC by reading PCI_HEADER_TYPE register. Like this:

pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
        printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
             ls_pcie_setup_ep(pcie);
} else {
        printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
             ls_pcie_setup_ctrl(pcie);
} 

Another issue is that, there are many share function will used by RC and EP driver,
so, if I separate the RC and EP driver, there will have many duplicate code. Like this:
dbi_readl, dbi_writel, ctrl_readl, ctrl_writel and so on.

> 
> Thanks,
> Ramon.
> 
> 
> > Thanks
> > Xiaowei
> >
> > >
> > > See
> > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpat
> > > chw
> > >
> ork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D104952&amp;da
> > >
> ta=02%7C01%7Cxiaowei.bao%40nxp.com%7Ca1e3da7d57a54520bd3008d6d
> > >
> a6fbc4d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C63693657
> > >
> 0769296107&amp;sdata=5CnEujEtYGbeiBEyv4iY5dXAapdQ65wCh1vs0quSVT
> > > Y%3D&amp;reserved=0
> > >
> > > Regards,
> > > Bin
Xiaowei Bao Nov. 25, 2019, 8:32 a.m. UTC | #8 
> -----Original Message-----
> From: Xiaowei Bao
> Sent: 2019年11月20日 11:28
> To: Ramon Fried <ramon.fried@gmail.com>
> Cc: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>;
> M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang
> <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> u-boot@lists.denx.de
> Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support
> for ls2088 PCIe EP mode
> 
> 
> 
> > -----Original Message-----
> > From: Ramon Fried <ramon.fried@gmail.com>
> > Sent: 2019年11月20日 2:50
> > To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > Cc: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>;
> > M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>;
> > Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang
> <hongbo.wang@nxp.com>;
> > York Sun <york.sun@nxp.com>; u-boot@lists.denx.de
> > Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > Support for ls2088 PCIe EP mode
> >
> > On Tue, Nov 19, 2019 at 5:27 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> > wrote:
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Xiaowei Bao
> > > > Sent: 2019年5月22日 18:19
> > > > To: Bin Meng <bmeng.cn@gmail.com>; Ramon Fried
> > > > <ramon.fried@gmail.com>; Simon Glass <sjg@chromium.org>
> > > > Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou
> > > > <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo
> > Wang
> > > > <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> > > > u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> > > > Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > > > Support for ls2088 PCIe EP mode
> > > >
> > > > Hi Bin,
> > > >
> > > > -----Original Message-----
> > > > From: Bin Meng <bmeng.cn@gmail.com>
> > > > Sent: 2019年5月17日 10:31
> > > > To: Xiaowei Bao <xiaowei.bao@nxp.com>; Ramon Fried
> > > > <ramon.fried@gmail.com>; Simon Glass <sjg@chromium.org>
> > > > Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou
> > > > <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo
> > Wang
> > > > <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> > > > u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> > > > Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > > > Support for ls2088 PCIe EP mode
> > > >
> > > > Caution: EXT Email
> > > >
> > > > Hi Xiaowei,
> > > >
> > > > On Fri, May 17, 2019 at 10:23 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > wrote:
> > > > >
> > > > >
> > > > >
> > > > > -----Original Message-----
> > > > > From: Bin Meng <bmeng.cn@gmail.com>
> > > > > Sent: 2019年5月16日 19:58
> > > > > To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > > Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou
> > > > > <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> Hongbo
> > > > Wang
> > > > > <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>;
> > > > > u-boot@lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> > > > > Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > > > > Support for ls2088 PCIe EP mode
> > > > >
> > > > > Caution: EXT Email
> > > > >
> > > > > Hi,
> > > > >
> > > > > On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao
> > > > > <xiaowei.bao@nxp.com>
> > > > wrote:
> > > > > >
> > > > > > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > > >
> > > > > > Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
> > > > > > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > > > ---
> > > > > > v2:
> > > > > >  - Add the NXP copyright and make the function readability.
> > > > > >
> > > > > >  drivers/pci/pcie_layerscape.c |  117
> > > > +++++++++++++++++++++++++++--------------
> > > > > >  drivers/pci/pcie_layerscape.h |   19 +++++--
> > > > > >  2 files changed, 91 insertions(+), 45 deletions(-)
> > > > > >
> > > > >
> > > > > Could you please support the PCIe EP mode using driver model?
> > > > > [Xiaowei Bao] do you mean that add a EP driver model to separate
> > > > > the RC
> > > > and EP with their respective drivers?
> > > >
> > > > That's correct.
> > > >
> > > > > The purpose of adding EP support under u-boot is to configure
> > > > > the size of the
> > > > BAR when the PCIE controller is used as an EP device, and to
> > > > ensure that the configuration space of the EP can be accessed, so
> > > > that when the RC scans the bus, the EP device can be scanned, and
> > > > we also can do simple MEM read and write verification through the
> > > > md command in
> > u-boot shell.
> > > > > When entering the kernel, the kernel has its own PCIE EP
> > > > > framework, which
> > > > will reinitialize the EP device, contain of the inbound and
> > > > outbound window configure, MSI configuration and so no.
> > > > >
> > > >
> > > > It's not kernel PCIe EP framework. Ramon Fried recently added PCIe
> > > > EP uclass support to U-Boot and you should add NXP layerscape PCIe
> > > > EP driver using the new EP uclass.
> > > > [Xiaowei Bao] OK, thanks, I will add NXP layerscape PCIe EP driver
> > > > using the new EP uclass.
> > >
> > > Hi Bin and Ramon,
> > >
> > > Do you know how to test the EP device when use Ramon Fried EP
> > > framework patch, I don't know how to use it in u-boot, take our
> > > board as an example, we use the RCW to configure the PCIe controller
> > > work as EP or RC, never use the DTS, another issue, when our PCIe
> > > controller work in EP mode, we must set this controller is ready
> > > before RC scan the bus, our main purpose is that set the BAR size
> > > and make it ready in u-boot, ensure that the EP controller is ready
> > > when enter the kernel or
> > other RC can scan the bus which the EP link, I am not sure whether
> > should separate the EP and RC driver. Do you have any advice?
> > >
> > In this case, where you need to initialize the EP as fast as possible,
> > you should define the dts node and probably add ""u-boot, dm-pre-reloc".
> > The you need to forcefully probe the EP in one of the pre-relocation
> > board callbacks.
> > This can be done by something like:
> > rc = uclass_get_device_by_name(UCLASS_PCI_EP, "pcie_ep@4800000",
> > &dev);:q
> 
> Thanks a lot, could you tell me when call the uclass_get_device_by_name
> function?
> 
> Actually, I am not very clear how to run the DM_TEST in test/dm/pci_ep.c
> maybe I need to learn more DM and UCLASS knowledge, if you can explain it, I
> will be very appreciate.

Hi Ramon,

I need your help on this, could you help explain how to start the PCIe EP test in
u-boot? Thanks a lot.

> 
> >
> > root complex and endpoint are totally different drivers, I don't see
> > how you can combine them together.
> 
> Thanks a lot form your comments, we combine the RC and EP driver in one
> file(drivers/pci/pcie_layerscape.c), and we run the different initialize code of
> EP and RC by reading PCI_HEADER_TYPE register. Like this:
> 
> pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
> if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
>         printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
>              ls_pcie_setup_ep(pcie);
> } else {
>         printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
>              ls_pcie_setup_ctrl(pcie);
> }
> 
> Another issue is that, there are many share function will used by RC and EP
> driver, so, if I separate the RC and EP driver, there will have many duplicate
> code. Like this:
> dbi_readl, dbi_writel, ctrl_readl, ctrl_writel and so on.
> 
> >
> > Thanks,
> > Ramon.
> >
> >
> > > Thanks
> > > Xiaowei
> > >
> > > >
> > > > See
> > > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fp
> > > > at
> > > > chw
> > > >
> >
> ork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D104952&amp;da
> > > >
> >
> ta=02%7C01%7Cxiaowei.bao%40nxp.com%7Ca1e3da7d57a54520bd3008d6d
> > > >
> >
> a6fbc4d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C63693657
> > > >
> >
> 0769296107&amp;sdata=5CnEujEtYGbeiBEyv4iY5dXAapdQ65wCh1vs0quSVT
> > > > Y%3D&amp;reserved=0
> > > >
> > > > Regards,
> > > > Bin
Ramon Fried Nov. 25, 2019, 12:15 p.m. UTC | #9 
>
> Hi Ramon,
>
> I need your help on this, could you help explain how to start the PCIe EP
> test in
> u-boot? Thanks a lot.
>
> Hi, you just need to run the test suite and it will test the PCIe EP
sandbox class automatically.
See test/README
Why do you care about the EP testing, it's testing the PCIe UCLASS
implementation.
To test your implementation you need to test on actual device.
Thanks,
Ramon.
Xiaowei Bao Nov. 26, 2019, 2:52 a.m. UTC | #10 
H Ramon,

Thanks for your comments.
If we reimplement the PCIe EP driver base on PCIe UCLASS, we must test it in u-boot, but I have no idea how to test the actual device, do I need to implement our own test case, how to verify the cadence-ep actual device?

Best regards
Xiaowei


From: Ramon Fried <ramon.fried@gmail.com>
Sent: 2019年11月25日 20:15
To: Xiaowei Bao <xiaowei.bao@nxp.com>
Cc: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>; M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>; u-boot@lists.denx.de
Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode



Hi Ramon,

I need your help on this, could you help explain how to start the PCIe EP test in
u-boot? Thanks a lot.
Hi, you just need to run the test suite and it will test the PCIe EP sandbox class automatically.
See test/README
Why do you care about the EP testing, it's testing the PCIe UCLASS implementation.
To test your implementation you need to test on actual device.
Thanks,
Ramon.
Xiaowei Bao Dec. 3, 2019, 2:32 a.m. UTC | #11 
Hi Ramon,

Do you have any comments about this? Thanks a lot.

Best regards
Xiaowei

From: Xiaowei Bao
Sent: 2019年11月26日 10:52
To: Ramon Fried <ramon.fried@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>; M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>; u-boot@lists.denx.de
Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode

H Ramon,

Thanks for your comments.
If we reimplement the PCIe EP driver base on PCIe UCLASS, we must test it in u-boot, but I have no idea how to test the actual device, do I need to implement our own test case, how to verify the cadence-ep actual device?

Best regards
Xiaowei


From: Ramon Fried <ramon.fried@gmail.com<mailto:ramon.fried@gmail.com>>
Sent: 2019年11月25日 20:15
To: Xiaowei Bao <xiaowei.bao@nxp.com<mailto:xiaowei.bao@nxp.com>>
Cc: Bin Meng <bmeng.cn@gmail.com<mailto:bmeng.cn@gmail.com>>; Simon Glass <sjg@chromium.org<mailto:sjg@chromium.org>>; M.h. Lian <minghuan.lian@nxp.com<mailto:minghuan.lian@nxp.com>>; Z.q. Hou <zhiqiang.hou@nxp.com<mailto:zhiqiang.hou@nxp.com>>; Mingkai Hu <mingkai.hu@nxp.com<mailto:mingkai.hu@nxp.com>>; Hongbo Wang <hongbo.wang@nxp.com<mailto:hongbo.wang@nxp.com>>; York Sun <york.sun@nxp.com<mailto:york.sun@nxp.com>>; u-boot@lists.denx.de<mailto:u-boot@lists.denx.de>
Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode



Hi Ramon,

I need your help on this, could you help explain how to start the PCIe EP test in
u-boot? Thanks a lot.
Hi, you just need to run the test suite and it will test the PCIe EP sandbox class automatically.
See test/README
Why do you care about the EP testing, it's testing the PCIe UCLASS implementation.
To test your implementation you need to test on actual device.
Thanks,
Ramon.
Ramon Fried Dec. 3, 2019, 8 p.m. UTC | #12 
On Tue, Dec 3, 2019 at 4:32 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
> Hi Ramon,
>
> Do you have any comments about this? Thanks a lot.
>
> Best regards
> Xiaowei
>
> From: Xiaowei Bao
> Sent: 2019年11月26日 10:52
> To: Ramon Fried <ramon.fried@gmail.com>
> Cc: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>; M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>; u-boot@lists.denx.de
> Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode
>
> H Ramon,
>
> Thanks for your comments.
> If we reimplement the PCIe EP driver base on PCIe UCLASS, we must test it in u-boot, but I have no idea how to test the actual device, do I need to implement our own test case, how to verify the cadence-ep actual device?
>
I'm not sure I understand what you're trying to achieve and why you're
referring to the cadence.
You're developing a driver, just test it against a client (IE. a real
PCIe root-complex).
The cadence is irrelevant, it's just another implementation of endpoint driver.
Thanks,
Ramon.
> Best regards
> Xiaowei
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
Xiaowei Bao Dec. 4, 2019, 2:23 a.m. UTC | #13 
> -----Original Message-----
> From: Ramon Fried <rfried.dev@gmail.com>
> Sent: 2019年12月4日 4:01
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: Ramon Fried <ramon.fried@gmail.com>; Hongbo Wang
> <hongbo.wang@nxp.com>; u-boot@lists.denx.de; York Sun
> <york.sun@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>
> Subject: Re: [U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add Support
> for ls2088 PCIe EP mode
> 
> On Tue, Dec 3, 2019 at 4:32 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> >
> > Hi Ramon,
> >
> > Do you have any comments about this? Thanks a lot.
> >
> > Best regards
> > Xiaowei
> >
> > From: Xiaowei Bao
> > Sent: 2019年11月26日 10:52
> > To: Ramon Fried <ramon.fried@gmail.com>
> > Cc: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>;
> > M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>;
> > Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang
> <hongbo.wang@nxp.com>;
> > York Sun <york.sun@nxp.com>; u-boot@lists.denx.de
> > Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > Support for ls2088 PCIe EP mode
> >
> > H Ramon,
> >
> > Thanks for your comments.
> > If we reimplement the PCIe EP driver base on PCIe UCLASS, we must test it
> in u-boot, but I have no idea how to test the actual device, do I need to
> implement our own test case, how to verify the cadence-ep actual device?
> >
> I'm not sure I understand what you're trying to achieve and why you're
> referring to the cadence.
> You're developing a driver, just test it against a client (IE. a real PCIe
> root-complex).
> The cadence is irrelevant, it's just another implementation of endpoint driver.

Thanks for your comments, do you mean that we can use the 'pci' and 'md' command
of u-boot to test the EP device when the controller which work as a EP device connect 
to a RC port, we can access the BAR base on the "pci header" command, yes? but if I want
to test memory access from EP to RC, what should I do, because there is not a command
which similar to 'pci' to test.

Another issue is that, due to the history reason of Layerscape PCIe controller driver, the
EP and RC codes are combined, if I separate the EP and RC code, there will have many
duplicate code.

Thanks
Xiaowei 


 
> Thanks,
> Ramon.
> > Best regards
> > Xiaowei
> > U-Boot@lists.denx.de
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> >
> s.denx.de%2Flistinfo%2Fu-boot&amp;data=02%7C01%7Cxiaowei.bao%40nxp
> .com
> > %7Cad7a366db91f4e40273308d7782b7fc8%7C686ea1d3bc2b4c6fa92cd99
> c5c301635
> > %7C0%7C0%7C637110000532938430&amp;sdata=T0D3QR5RzdFv96syOlG
> VK7OEBQyNdl
> > 8M9pfd%2F4vxOIg%3D&amp;reserved=0
Ramon Fried Dec. 4, 2019, 7:33 a.m. UTC | #14 
On Wed, Dec 4, 2019 at 4:23 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Ramon Fried <rfried.dev@gmail.com>
> > Sent: 2019年12月4日 4:01
> > To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > Cc: Ramon Fried <ramon.fried@gmail.com>; Hongbo Wang
> > <hongbo.wang@nxp.com>; u-boot@lists.denx.de; York Sun
> > <york.sun@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu
> > <mingkai.hu@nxp.com>
> > Subject: Re: [U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add Support
> > for ls2088 PCIe EP mode
> >
> > On Tue, Dec 3, 2019 at 4:32 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> > >
> > > Hi Ramon,
> > >
> > > Do you have any comments about this? Thanks a lot.
> > >
> > > Best regards
> > > Xiaowei
> > >
> > > From: Xiaowei Bao
> > > Sent: 2019年11月26日 10:52
> > > To: Ramon Fried <ramon.fried@gmail.com>
> > > Cc: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>;
> > > M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>;
> > > Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang
> > <hongbo.wang@nxp.com>;
> > > York Sun <york.sun@nxp.com>; u-boot@lists.denx.de
> > > Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > > Support for ls2088 PCIe EP mode
> > >
> > > H Ramon,
> > >
> > > Thanks for your comments.
> > > If we reimplement the PCIe EP driver base on PCIe UCLASS, we must test it
> > in u-boot, but I have no idea how to test the actual device, do I need to
> > implement our own test case, how to verify the cadence-ep actual device?
> > >
> > I'm not sure I understand what you're trying to achieve and why you're
> > referring to the cadence.
> > You're developing a driver, just test it against a client (IE. a real PCIe
> > root-complex).
> > The cadence is irrelevant, it's just another implementation of endpoint driver.
>
> Thanks for your comments, do you mean that we can use the 'pci' and 'md' command
> of u-boot to test the EP device when the controller which work as a EP device connect
> to a RC port, we can access the BAR base on the "pci header" command, yes? but if I want
> to test memory access from EP to RC, what should I do, because there is not a command
> which similar to 'pci' to test.
>
No, I don't mean that. Currently there's no cmd line interface for
PCIe endpoint (patches welcome).
You should test the driver against a *real* setup, where you configure
the endpoint using some init function
in the board startup sequence.


> Another issue is that, due to the history reason of Layerscape PCIe controller driver, the
> EP and RC codes are combined, if I separate the EP and RC code, there will have many
> duplicate code.
So create a common.c file for both of them.
>
> Thanks
> Xiaowei
>
>
>
> > Thanks,
> > Ramon.
> > > Best regards
> > > Xiaowei
> > > U-Boot@lists.denx.de
> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > >
> > s.denx.de%2Flistinfo%2Fu-boot&amp;data=02%7C01%7Cxiaowei.bao%40nxp
> > .com
> > > %7Cad7a366db91f4e40273308d7782b7fc8%7C686ea1d3bc2b4c6fa92cd99
> > c5c301635
> > > %7C0%7C0%7C637110000532938430&amp;sdata=T0D3QR5RzdFv96syOlG
> > VK7OEBQyNdl
> > > 8M9pfd%2F4vxOIg%3D&amp;reserved=0
Xiaowei Bao Dec. 5, 2019, 7:02 a.m. UTC | #15 
> -----Original Message-----
> From: Ramon Fried <rfried.dev@gmail.com>
> Sent: 2019年12月4日 15:34
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: Ramon Fried <ramon.fried@gmail.com>; Hongbo Wang
> <hongbo.wang@nxp.com>; u-boot@lists.denx.de; York Sun
> <york.sun@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>
> Subject: Re: [U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add Support
> for ls2088 PCIe EP mode
> 
> On Wed, Dec 4, 2019 at 4:23 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Ramon Fried <rfried.dev@gmail.com>
> > > Sent: 2019年12月4日 4:01
> > > To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Cc: Ramon Fried <ramon.fried@gmail.com>; Hongbo Wang
> > > <hongbo.wang@nxp.com>; u-boot@lists.denx.de; York Sun
> > > <york.sun@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu
> > > <mingkai.hu@nxp.com>
> > > Subject: Re: [U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add
> > > Support for ls2088 PCIe EP mode
> > >
> > > On Tue, Dec 3, 2019 at 4:32 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> wrote:
> > > >
> > > > Hi Ramon,
> > > >
> > > > Do you have any comments about this? Thanks a lot.
> > > >
> > > > Best regards
> > > > Xiaowei
> > > >
> > > > From: Xiaowei Bao
> > > > Sent: 2019年11月26日 10:52
> > > > To: Ramon Fried <ramon.fried@gmail.com>
> > > > Cc: Bin Meng <bmeng.cn@gmail.com>; Simon Glass
> <sjg@chromium.org>;
> > > > M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou
> > > > <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo
> > > > Wang
> > > <hongbo.wang@nxp.com>;
> > > > York Sun <york.sun@nxp.com>; u-boot@lists.denx.de
> > > > Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > > > Support for ls2088 PCIe EP mode
> > > >
> > > > H Ramon,
> > > >
> > > > Thanks for your comments.
> > > > If we reimplement the PCIe EP driver base on PCIe UCLASS, we must
> > > > test it
> > > in u-boot, but I have no idea how to test the actual device, do I
> > > need to implement our own test case, how to verify the cadence-ep
> actual device?
> > > >
> > > I'm not sure I understand what you're trying to achieve and why
> > > you're referring to the cadence.
> > > You're developing a driver, just test it against a client (IE. a
> > > real PCIe root-complex).
> > > The cadence is irrelevant, it's just another implementation of endpoint
> driver.
> >
> > Thanks for your comments, do you mean that we can use the 'pci' and
> > 'md' command of u-boot to test the EP device when the controller which
> > work as a EP device connect to a RC port, we can access the BAR base
> > on the "pci header" command, yes? but if I want to test memory access
> > from EP to RC, what should I do, because there is not a command which
> similar to 'pci' to test.
> >
> No, I don't mean that. Currently there's no cmd line interface for PCIe
> endpoint (patches welcome).
> You should test the driver against a *real* setup, where you configure the
> endpoint using some init function in the board startup sequence.

OK, thanks for your comments.

> 
> 
> > Another issue is that, due to the history reason of Layerscape PCIe
> > controller driver, the EP and RC codes are combined, if I separate the
> > EP and RC code, there will have many duplicate code.
> So create a common.c file for both of them.
> >
> > Thanks
> > Xiaowei
> >
> >
> >
> > > Thanks,
> > > Ramon.
> > > > Best regards
> > > > Xiaowei
> > > > U-Boot@lists.denx.de
> > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > > > list
> > > >
> > >
> s.denx.de%2Flistinfo%2Fu-boot&amp;data=02%7C01%7Cxiaowei.bao%40nxp
> > > .com
> > > > %7Cad7a366db91f4e40273308d7782b7fc8%7C686ea1d3bc2b4c6fa92c
> d99
> > > c5c301635
> > > > %7C0%7C0%7C637110000532938430&amp;sdata=T0D3QR5RzdFv96sy
> OlG
> > > VK7OEBQyNdl
> > > > 8M9pfd%2F4vxOIg%3D&amp;reserved=0
diff mbox series

Patch

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index db1375a..8f5ebda 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,6 +1,6 @@ 
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017 NXP
+ * Copyright 2017, 2019 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  */
@@ -105,13 +105,14 @@  static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
 }
 
 /* Use bar match mode and MEM type as default */
-static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
-				     int bar, u64 phys)
+static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int idx,
+				    int bar, u64 phys)
 {
 	dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
 	dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
 	dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
-	dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
+	dbi_writel(pcie, PCIE_ATU_TYPE_MEM | PCIE_CTRL1_FUNC_NUM(pf),
+		   PCIE_ATU_CR1);
 	dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
 		   PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
 }
@@ -341,50 +342,61 @@  static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
 	ls_pcie_disable_bars(pcie);
 }
 
-static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
+static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie, u32 pf)
 {
-	u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
+	pci_size_t atu_size = CONFIG_SYS_PCI_MEMORY_SIZE;
+	u64 phys = 0;
 
+	phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_2M;
+
+	phys = ALIGN(phys, PCIE_BAR0_SIZE);
 	/* ATU 0 : INBOUND : map BAR0 */
-	ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
+	ls_pcie_atu_inbound_set(pcie, pf, 0 + pf * BAR_NUM, 0, phys);
 	/* ATU 1 : INBOUND : map BAR1 */
-	phys += PCIE_BAR1_SIZE;
-	ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
+	phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE);
+	ls_pcie_atu_inbound_set(pcie, pf, 1 + pf * BAR_NUM, 1, phys);
 	/* ATU 2 : INBOUND : map BAR2 */
-	phys += PCIE_BAR2_SIZE;
-	ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
-	/* ATU 3 : INBOUND : map BAR4 */
-	phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
-	ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
+	phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE);
+	ls_pcie_atu_inbound_set(pcie, pf, 2 + pf * BAR_NUM, 2, phys);
+	/* ATU 3 : INBOUND : map BAR2 */
+	phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR2_SIZE);
+	ls_pcie_atu_inbound_set(pcie, pf, 3 + pf * BAR_NUM, 4, phys);
 
 	/* ATU 0 : OUTBOUND : map MEM */
-	ls_pcie_atu_outbound_set(pcie, 0,
-				 PCIE_ATU_TYPE_MEM,
-				 pcie->cfg_res.start,
-				 0,
-				 CONFIG_SYS_PCI_MEMORY_SIZE);
+	ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
+				 PCIE_ATU_TYPE_MEM, (u64)pcie->cfg_res.start,
+				 0, atu_size);
+
+	/* ATU 1 : OUTBOUND : map MEM */
+	ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
+				 PCIE_ATU_TYPE_MEM, (u64)pcie->cfg_res.start
+				 + atu_size, atu_size, atu_size);
 }
 
 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
 static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
 {
+	u32 mask;
+
 	/* The least inbound window is 4KiB */
-	if (size < 4 * 1024)
-		return;
+	if (size < SZ_4K)
+		mask = 0;
+	else
+		mask = size - 1;
 
 	switch (bar) {
 	case 0:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
+		writel(mask, bar_base + PCI_BASE_ADDRESS_0);
 		break;
 	case 1:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
+		writel(mask, bar_base + PCI_BASE_ADDRESS_1);
 		break;
 	case 2:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
+		writel(mask, bar_base + PCI_BASE_ADDRESS_2);
 		writel(0, bar_base + PCI_BASE_ADDRESS_3);
 		break;
 	case 4:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
+		writel(mask, bar_base + PCI_BASE_ADDRESS_4);
 		writel(0, bar_base + PCI_BASE_ADDRESS_5);
 		break;
 	default:
@@ -394,13 +406,28 @@  static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
 
 static void ls_pcie_ep_setup_bars(void *bar_base)
 {
-	/* BAR0 - 32bit - 4K configuration */
+	/* BAR0 - 32bit - configuration */
+	ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
+	/* BAR1 - 32bit - MSIX*/
+	ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
+	/* BAR2 - 64bit - MEM descriptor */
+	ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
+	/* BAR4 - 64bit - MEM*/
+	ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
+}
+
+static void ls_pcie_ep_setup_vf_bars(void *bar_base)
+{
+	/* VF BAR0 MASK register at offset 0x19c*/
+	bar_base += PCIE_SRIOV_VFBAR0 - PCI_BASE_ADDRESS_0;
+
+	/* VF-BAR0 - 32bit - configuration */
 	ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
-	/* BAR1 - 32bit - 8K MSIX*/
+	/* VF-BAR1 - 32bit - MSIX*/
 	ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
-	/* BAR2 - 64bit - 4K MEM desciptor */
+	/* VF-BAR2 - 64bit - MEM descriptor */
 	ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
-	/* BAR4 - 64bit - 1M MEM*/
+	/* VF-BAR4 - 64bit - MEM*/
 	ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
 }
 
@@ -412,25 +439,33 @@  static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
 static void ls_pcie_setup_ep(struct ls_pcie *pcie)
 {
 	u32 sriov;
+	u32 pf, vf;
+	void *bar_base = NULL;
 
 	sriov = readl(pcie->dbi + PCIE_SRIOV);
 	if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
-		int pf, vf;
-
+		pcie->sriov_flag = 1;
 		for (pf = 0; pf < PCIE_PF_NUM; pf++) {
-			for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
-				ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
-					    PCIE_PF_VF_CTRL);
-
-				ls_pcie_ep_setup_bars(pcie->dbi);
-				ls_pcie_ep_setup_atu(pcie);
+			if (pcie->cfg2_flag) {
+				for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+					ctrl_writel(pcie,
+						    PCIE_LCTRL0_VAL(pf, vf),
+						    PCIE_PF_VF_CTRL);
+				}
 			}
+			bar_base = pcie->dbi +
+				   PCIE_MASK_OFFSET(pcie->cfg2_flag, pf);
+			ls_pcie_ep_setup_bars(bar_base);
+			ls_pcie_ep_setup_vf_bars(bar_base);
+
+			ls_pcie_ep_setup_atu(pcie, pf);
 		}
-		/* Disable CFG2 */
-		ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
+
+		if (pcie->cfg2_flag)  /* Disable CFG2 */
+			ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
 	} else {
 		ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
-		ls_pcie_ep_setup_atu(pcie);
+		ls_pcie_ep_setup_atu(pcie, 0);
 	}
 
 	ls_pcie_ep_enable_cfg(pcie);
@@ -502,6 +537,7 @@  static int ls_pcie_probe(struct udevice *dev)
 	 * for LS2088A series SoCs
 	 */
 	svr = get_svr();
+	pcie->cfg2_flag = 1;
 	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
@@ -511,6 +547,7 @@  static int ls_pcie_probe(struct udevice *dev)
 					LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 		pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
 		pcie->ctrl = pcie->lut + 0x40000;
+		pcie->cfg2_flag = 0;
 	}
 
 	pcie->cfg0 = map_physmem(pcie->cfg_res.start,
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index ddfbba6..eb910ba 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -1,6 +1,6 @@ 
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017 NXP
+ * Copyright 2017, 2019 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  */
@@ -9,6 +9,7 @@ 
 #define _PCIE_LAYERSCAPE_H_
 #include <pci.h>
 #include <dm.h>
+#include <linux/sizes.h>
 
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
@@ -85,11 +86,17 @@ 
 
 #define PCIE_PF_NUM		2
 #define PCIE_VF_NUM		64
+#define BAR_NUM			4
 
-#define PCIE_BAR0_SIZE		(4 * 1024) /* 4K */
-#define PCIE_BAR1_SIZE		(8 * 1024) /* 8K for MSIX */
-#define PCIE_BAR2_SIZE		(4 * 1024) /* 4K */
-#define PCIE_BAR4_SIZE		(1 * 1024 * 1024) /* 1M */
+#define PCIE_BAR0_SIZE		SZ_4K /* 4K */
+#define PCIE_BAR1_SIZE		SZ_8K /* 8K for MSIX */
+#define PCIE_BAR2_SIZE		SZ_4K /* 4K */
+#define PCIE_BAR4_SIZE		SZ_1M /* 1M */
+
+#define PCIE_SRIOV_VFBAR0	0x19C
+#define PCIE_CTRL1_FUNC_NUM(pf)	(pf << 20)
+
+#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x20000 * (pf)))
 
 /* LUT registers */
 #define PCIE_LUT_UDR(n)		(0x800 + (n) * 8)
@@ -144,6 +151,8 @@  struct ls_pcie {
 	bool big_endian;
 	bool enabled;
 	int next_lut_index;
+	uint sriov_flag;
+	uint cfg2_flag;
 	int mode;
 };