From patchwork Tue Apr 30 10:06:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1093130 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44tchm3Xprz9sBr for ; Tue, 30 Apr 2019 20:10:00 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1FF07C21E07; Tue, 30 Apr 2019 10:08:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 324F2C21E0B; Tue, 30 Apr 2019 10:07:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 89A0DC21E1D; Tue, 30 Apr 2019 10:07:09 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lists.denx.de (Postfix) with ESMTPS id 529CBC21E0B for ; Tue, 30 Apr 2019 10:07:07 +0000 (UTC) Received: from marcel-nb-toradex-int.toradex.int ([46.140.72.82]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0Mgv7W-1h8GWN1GXQ-00M7R4; Tue, 30 Apr 2019 12:06:47 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Tue, 30 Apr 2019 12:06:26 +0200 Message-Id: <20190430100629.9212-4-marcel@ziswiler.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430100629.9212-1-marcel@ziswiler.com> References: <20190430100629.9212-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:e8UYQCHLHnqgxEBKh7gcsSwTAi5RmqjEnKC4XYmvYVYP8hiYWZT 8lJNWrgrrUHo0ySZKXFG4TnWdoEtL0VxpxMZ09ZofVFKfZy5LbQi20GVjfYSsjn2e+8BcM6 9A9i+M1Nm9eY2PVDwbCGeo1nOcJjOrwdzupNbuJqC8Jlz1I9HiVF1uqOREW73NEiruXcVYQ IUcy8fL0++ENHX03Txiyw== X-UI-Out-Filterresults: notjunk:1; V03:K0:NQ/paGJ4jjM=:kUDv5/KPVTumgC7uA4qt4K AyZ8Q+8g2692yN9zxFSKljYJ7bbPQThJh4CvWlJqcqdIQxC5KBdqKZAEez0c7TZy1SRNgH3BY u7Pycl4EKyp0ShuhqChKb8WlvkXTNJYqYlBDsgOp+zqGWSd9yRfNbydPm1EI4HEs6tCegVUqj +hfwxNcD5x7pWXeh7ZHiP7Jc6KEY5+Ec7+Q+oFGlpMLxbTr4pj+8EjNhWYw5ujIFdm0o1peuQ +OaET7v+yajgh/RRoVgn9Z1GPDXx3/IvIQzQI3Jo6sN4xN0r5FGqGlMurFRIyXIKwjaekExH6 aTgnhw3/Q63n+Pw8ZUnEICmi7LFE9t2tidRBRMn7REgkggqC2WwHklqPdF5qDNbxAaa44U5nf FiZfIbwiXKcrBm6tgDrvYQh8vzhh3L619F7wuxD9inceeDMETFs6ZKu1P+MsouAKJbbNfz/h2 yrkgdAIAN/Xn1X0HBoLBpvBEo5uLF1GETTef95Osbfi0XeTHGQpPhO3i3N6YHS9HaKQW3N6vD 06+ejiA3d7mXKl9xkNn4/z/ault/Cg9qJHDgRa7nQI9bfUx2G4pzBmeBQcOxsE+To7gvRlKQC 0nuldZSbkGmydujG1SHG/guoc48ElxEdUBLsw7GnVY9vfouqQEJqGcopsbtSIJFJl2qjEria1 GvktP7WbpoKnMBfb/co24L3dkLgFsaJYOT+IBo8jhVQIdVGHWzbk9lNczIT9MN7xYajji+4oC o4LMtRt7Emlau39/a2qnoFpy47ZRa8PE+9egmQ== Cc: Tom Rini , Marcel Ziswiler , Marcel Ziswiler , Fabio Estevam Subject: [U-Boot] [PATCH 3/6] clk: imx8qm: fix usdhc2 clocks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Trying to bring up uSDHC2 the following error message was observed: MMC: imx8_clk_set_rate(Invalid clk ID #60) imx8_clk_set_rate(Invalid clk ID #60) usdhc@5b030000 - probe failed: -22 This commit fixes this by properly setting resp. clocks. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- drivers/clk/imx/clk-imx8qm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 6b5561e178..a6b09d2109 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -80,6 +80,12 @@ ulong imx8_clk_get_rate(struct clk *clk) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_UART0_IPG_CLK: case IMX8QM_UART0_CLK: resource = SC_R_UART_0; @@ -185,6 +191,12 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_ENET0_IPG_CLK: case IMX8QM_ENET0_AHB_CLK: case IMX8QM_ENET0_REF_DIV: @@ -273,6 +285,12 @@ int __imx8_clk_enable(struct clk *clk, bool enable) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_ENET0_IPG_CLK: case IMX8QM_ENET0_AHB_CLK: case IMX8QM_ENET0_REF_DIV: