From patchwork Fri Apr 26 03:59:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1091217 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="HO1LegHq"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44r0yn4LrGz9s3l for ; Fri, 26 Apr 2019 14:13:05 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 48302C21E44; Fri, 26 Apr 2019 04:06:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 38713C21E4E; Fri, 26 Apr 2019 04:01:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1097FC21D65; Fri, 26 Apr 2019 04:00:35 +0000 (UTC) Received: from mail-it1-f193.google.com (mail-it1-f193.google.com [209.85.166.193]) by lists.denx.de (Postfix) with ESMTPS id 26A9FC21E3A for ; Fri, 26 Apr 2019 04:00:32 +0000 (UTC) Received: by mail-it1-f193.google.com with SMTP id q14so3777650itk.0 for ; Thu, 25 Apr 2019 21:00:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6xNnHR+cfDuUwez46Apu4IgWKn/NECwSA2hIsKS1H9g=; b=HO1LegHqzxhOch7D7Btgrutfs9ktX95mM+bFqrQMwLzQft+G5rlqQg8KbrVe2FNGlj d0vg8XtbnJ+5wDpgAEbwpbraZ+7oEgEMDWsWntqA8gZAxEHUm8Y71TeJWyQ7rwajOBlz fmRdI07jValCnmRLDWlOnVbdKksXkDMB+6wKk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6xNnHR+cfDuUwez46Apu4IgWKn/NECwSA2hIsKS1H9g=; b=WUj/B8yZGtFJjasXD7rEji+kfVPThntRCZfsGzEI7Rgfpkoi1KpZs8/2Ng9lJqG5F7 ynBACag/Ymy2apAoj3Lv3lZqC0ob7B9LJkgN1QcSOMs/bmZd3P/GO7CzQvf6V9kM8UJq TdboYSnRTIto/WyFW4+w4rYMvAlKQN/SBCioc2BqbCnjKPma+Nkqm0JLxefKfAfLW9bU DzzcweYzLyLrP/loyF1raQF9Ei31dk0mfiI9uLytHjXe/yWgc37KCniXfxDSkavw+GR8 drPHjryfPoWu9Pf3hXrTQcmjp2QcV3wBl3fCC9uxzeuJAoISRP8PDoKzNlcMOUSEi8it 0OGA== X-Gm-Message-State: APjAAAVsA8EJ36J+fhYuua9aGkpBxt7bEWJjEsuHpT5fu/vNeKnq7EOJ i1g7VZCIAae08I4uZ0DwZc8oKHQYZ94= X-Google-Smtp-Source: APXvYqyda9L8f3gjJOKBbc74RQY1prqC16E94KiqHWRRaDcvwRu5y3chURzPdI4mkCztTxs3C63CAw== X-Received: by 2002:a24:758a:: with SMTP id y132mr6592923itc.69.1556251230998; Thu, 25 Apr 2019 21:00:30 -0700 (PDT) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id m142sm5006180itb.31.2019.04.25.21.00.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 21:00:30 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Thu, 25 Apr 2019 21:59:15 -0600 Message-Id: <20190426035922.20596-44-sjg@chromium.org> X-Mailer: git-send-email 2.21.0.593.g511ec345e18-goog In-Reply-To: <20190426035922.20596-1-sjg@chromium.org> References: <20190426035922.20596-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v2 43/50] x86: Fix device-tree indentation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" With the use of a phandle we can outdent the device tree nodes a little. Fix this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v2: None arch/x86/dts/u-boot.dtsi | 147 +++++++++++++++++++-------------------- 1 file changed, 73 insertions(+), 74 deletions(-) diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 5943619b863..8bb1318a2ce 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -23,104 +23,103 @@ #ifdef CONFIG_ROM_SIZE &rom { - filename = "u-boot.rom"; - end-at-4gb; - sort-by-offset; - pad-byte = <0xff>; - size = ; + filename = "u-boot.rom"; + end-at-4gb; + sort-by-offset; + pad-byte = <0xff>; + size = ; #ifdef CONFIG_HAVE_INTEL_ME - intel-descriptor { - filename = CONFIG_FLASH_DESCRIPTOR_FILE; - }; - intel-me { - filename = CONFIG_INTEL_ME_FILE; - }; + intel-descriptor { + filename = CONFIG_FLASH_DESCRIPTOR_FILE; + }; + intel-me { + filename = CONFIG_INTEL_ME_FILE; + }; #endif #ifdef CONFIG_TPL - u-boot-spl { - offset = ; - }; - u-boot-spl-dtb { - }; - u-boot-tpl-with-ucode-ptr { - offset = ; - }; - u-boot-tpl-dtb { - }; - u-boot { - offset = ; - }; + u-boot-spl { + offset = ; + }; + u-boot-spl-dtb { + }; + u-boot-tpl-with-ucode-ptr { + offset = ; + }; + u-boot-tpl-dtb { + }; + u-boot { + offset = ; + }; #elif defined(CONFIG_SPL) - u-boot-spl-with-ucode-ptr { - offset = ; - }; - - u-boot-dtb-with-ucode2 { - type = "u-boot-dtb-with-ucode"; - }; - u-boot { + u-boot-spl-with-ucode-ptr { + offset = ; + }; + u-boot-dtb-with-ucode2 { + type = "u-boot-dtb-with-ucode"; + }; + u-boot { #if CONFIG_SYS_TEXT_BASE == 0x1110000 - offset = <0xfff00000>; + offset = <0xfff00000>; #else - offset = ; + offset = ; #endif - }; + }; #else - u-boot-with-ucode-ptr { - offset = ; - }; + u-boot-with-ucode-ptr { + offset = ; + }; #endif - u-boot-dtb-with-ucode { - }; - u-boot-ucode { - align = <16>; - }; + u-boot-dtb-with-ucode { + }; + u-boot-ucode { + align = <16>; + }; #ifdef CONFIG_HAVE_MRC - intel-mrc { - offset = ; - }; + intel-mrc { + offset = ; + }; #endif #ifdef CONFIG_HAVE_FSP - intel-fsp { - filename = CONFIG_FSP_FILE; - offset = ; - }; + intel-fsp { + filename = CONFIG_FSP_FILE; + offset = ; + }; #endif #ifdef CONFIG_HAVE_CMC - intel-cmc { - filename = CONFIG_CMC_FILE; - offset = ; - }; + intel-cmc { + filename = CONFIG_CMC_FILE; + offset = ; + }; #endif #ifdef CONFIG_HAVE_VGA_BIOS - intel-vga { - filename = CONFIG_VGA_BIOS_FILE; - offset = ; - }; + intel-vga { + filename = CONFIG_VGA_BIOS_FILE; + offset = ; + }; #endif #ifdef CONFIG_HAVE_VBT - intel-vbt { - filename = CONFIG_VBT_FILE; - offset = ; - }; + intel-vbt { + filename = CONFIG_VBT_FILE; + offset = ; + }; #endif #ifdef CONFIG_HAVE_REFCODE - intel-refcode { - offset = ; - }; + intel-refcode { + offset = ; + }; #endif #ifdef CONFIG_TPL - x86-start16-tpl { - offset = ; - }; + x86-start16-tpl { + offset = ; + }; #elif defined(CONFIG_SPL) - x86-start16-spl { - offset = ; - }; + x86-start16-spl { + offset = ; + }; #else - x86-start16 { - offset = ; - }; + x86-start16 { + offset = ; + }; #endif }; #endif