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[86.49.110.70]) by smtp.gmail.com with ESMTPSA id w2sm8301408wrm.74.2019.04.21.15.20.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Apr 2019 15:20:40 -0700 (PDT) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Mon, 22 Apr 2019 00:20:19 +0200 Message-Id: <20190421222021.22494-3-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190421222021.22494-1-marek.vasut+renesas@gmail.com> References: <20190421222021.22494-1-marek.vasut+renesas@gmail.com> MIME-Version: 1.0 Cc: Eugeniu Rosca , Marek Vasut Subject: [U-Boot] [PATCH 3/5] pinctrl: renesas: Implement gpio_request_enable/gpio_disable_free X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement the gpio_request_enable/gpio_disable_free callbacks to let the GPIO driver call the pin control framework and let it reconfigure pins as GPIOs. Signed-off-by: Marek Vasut Cc: Alex Kiernan Cc: Christoph Muellner Cc: Eugeniu Rosca Cc: Patrice Chotard Cc: Patrick DELAUNAY Cc: Philipp Tomsich Cc: Simon Glass Reviewed-by: Eugeniu Rosca Tested-by: Eugeniu Rosca --- drivers/pinctrl/renesas/pfc.c | 40 ++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 59dc4af702..52c486ebc2 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -459,7 +459,8 @@ static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev, return priv->pfc.info->functions[selector].name; } -int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector) +static int sh_pfc_gpio_request_enable(struct udevice *dev, + unsigned pin_selector) { struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); struct sh_pfc_pinctrl *pmx = &priv->pmx; @@ -494,6 +495,40 @@ int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector) return 0; } +static int sh_pfc_gpio_disable_free(struct udevice *dev, + unsigned pin_selector) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + struct sh_pfc_pin_config *cfg; + const struct sh_pfc_pin *pin = NULL; + int i, idx; + + for (i = 1; i < pfc->info->nr_pins; i++) { + if (priv->pfc.info->pins[i].pin != pin_selector) + continue; + + pin = &priv->pfc.info->pins[i]; + break; + } + + if (!pin) + return -EINVAL; + + idx = sh_pfc_get_pin_index(pfc, pin->pin); + cfg = &pmx->configs[idx]; + + cfg->type = PINMUX_TYPE_NONE; + + return 0; +} + +int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector) +{ + return sh_pfc_gpio_request_enable(dev, pin_selector); +} + static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, unsigned func_selector) { @@ -752,6 +787,9 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = { .pinmux_set = sh_pfc_pinctrl_pin_set, .pinmux_group_set = sh_pfc_pinctrl_group_set, .set_state = pinctrl_generic_set_state, + + .gpio_request_enable = sh_pfc_gpio_request_enable, + .gpio_disable_free = sh_pfc_gpio_disable_free, }; static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)