Message ID | 20190329144831.3179-3-kever.yang@rock-chips.com |
---|---|
State | Accepted |
Commit | 4d9dd40d68e4d1fbe170ade90e36753ff259ffca |
Delegated to: | Kever Yang |
Headers | show |
Series | rockchip: enable spl/tpl for px5-evb | expand |
Kever Yang <kever.yang@rock-chips.com> 于2019年3月29日周五 下午10:52写道: > TPL need dmc to init ddr sdram, and emmc, boot-order. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > --- > > arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 29 +++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > Tested-by: Andy Yan <andy.yan@rock-chips.com> > diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi > b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi > index 7495781454..18b841864c 100644 > --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi > +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi > @@ -2,6 +2,27 @@ > /* > * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH > */ > +/ { > + chosen { > + u-boot,spl-boot-order = &emmc; > + }; > +}; > + > +&dmc { > + u-boot,dm-pre-reloc; > + > + /* > + * PX5-evb(2GB) need to use CBRD mode, or else the dram is not > correct > + * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for > + * details on the 'rockchip,memory-schedule' property and how it > + * affects the physical-address to device-address mapping. > + */ > + rockchip,memory-schedule = <DMC_MSCH_CBRD>; > + rockchip,ddr-frequency = <800000000>; > + rockchip,ddr-speed-bin = <DDR3_1600K>; > + > + status = "okay"; > +}; > > &pinctrl { > u-boot,dm-pre-reloc; > @@ -20,6 +41,10 @@ > u-boot,dm-pre-reloc; > }; > > +&sgrf { > + u-boot,dm-pre-reloc; > +}; > + > &cru { > u-boot,dm-pre-reloc; > }; > @@ -31,3 +56,7 @@ > &uart4 { > u-boot,dm-pre-reloc; > }; > + > +&emmc { > + u-boot,dm-pre-reloc; > +}; > -- > 2.20.1 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot >
diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi index 7495781454..18b841864c 100644 --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -2,6 +2,27 @@ /* * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +/ { + chosen { + u-boot,spl-boot-order = &emmc; + }; +}; + +&dmc { + u-boot,dm-pre-reloc; + + /* + * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct + * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for + * details on the 'rockchip,memory-schedule' property and how it + * affects the physical-address to device-address mapping. + */ + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + rockchip,ddr-frequency = <800000000>; + rockchip,ddr-speed-bin = <DDR3_1600K>; + + status = "okay"; +}; &pinctrl { u-boot,dm-pre-reloc; @@ -20,6 +41,10 @@ u-boot,dm-pre-reloc; }; +&sgrf { + u-boot,dm-pre-reloc; +}; + &cru { u-boot,dm-pre-reloc; }; @@ -31,3 +56,7 @@ &uart4 { u-boot,dm-pre-reloc; }; + +&emmc { + u-boot,dm-pre-reloc; +};
TPL need dmc to init ddr sdram, and emmc, boot-order. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> --- arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 29 +++++++++++++++++++++++++ 1 file changed, 29 insertions(+)