Message ID | 20190325073520.452-5-uboot@andestech.com |
---|---|
State | Superseded |
Delegated to: | Andes |
Headers | show |
Series | AE350 SMP support RISC-V | expand |
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index e9dbca2..68bd4e9 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -1,5 +1,11 @@ config RISCV_NDS bool + select ARCH_EARLY_INIT_R + imply CPU + imply CPU_RISCV + imply RISCV_TIMER + imply ANDES_PLIC if RISCV_MMODE + imply ANDES_PLMT if RISCV_MMODE help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families.