From patchwork Thu Mar 21 17:14:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1060301 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YTz2xzKC"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44QD1722X9z9sRG for ; Fri, 22 Mar 2019 04:14:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id EEAB5C220C2; Thu, 21 Mar 2019 17:14:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7DFEFC2203D; Thu, 21 Mar 2019 17:14:29 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3BCD2C22036; Thu, 21 Mar 2019 17:14:27 +0000 (UTC) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by lists.denx.de (Postfix) with ESMTPS id B8D74C21C2F for ; Thu, 21 Mar 2019 17:14:26 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id w1so7528564wrp.2 for ; Thu, 21 Mar 2019 10:14:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=fde2LjiK1m4Rs7oPSn/qtm8DNPFOh/fBJAVgWq/YxzE=; b=YTz2xzKCMx2zXD+fL9Ox5f9FqFgKxLE6oxl3kFpqAdPw9xO8dviYfJSjSz7pbALbCU 5vRVC8NE2fBHT/6M/+uWdJPfZJnH4maxM6BnMdHDljBOjMR8KpxROWA0tcaawJtBt1Zl VvYrcpeF/ImRfHuPnZY+7/x/9ipnEWMUaVDMEAUFkQXz8zCKwAX0W8mc2fwfu0gTWDyx BMv4YuU8n+yyPqShHkjhTNcqat2wSkzPTcYpetDWY5mD6Ipdr5SWdZCegVf2V42FG3Eh gSf935Kpp3/P3YNsx5520hGN28yHCUQMOSmWS9AckZlNwPmr4KcW8upYGOIWZDgCyX2/ gVNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=fde2LjiK1m4Rs7oPSn/qtm8DNPFOh/fBJAVgWq/YxzE=; b=GbA8D5LY6I2a2mgGV38b1eZgEP+PNc12TSvzpgNXICCjujb50nop0pB4rSYTHTmmpT Er6Wy3LWuyNWP3KB2yFV7JO6wnYFRVPoDGfRkF426Az2kjHy2Sf/JRMcXazDeK6FYAdf c9TqxyRVaJBdgH5qCHkjGNCDkab35t3IDOvJrCNfn6kYp1lqI4ExGDrVKH3y/TIiTKKu 2j3QzM20Xm78iFfBuxO7IeOFZtoluaosIv21LIbG9qlp8sgRK3PqMbMeYfcHOO72IX66 wUCNwYaWRngaprLURYYVDmkYufJqyp/CEzkdncTJNCx25iMdNjbZ43gZ5C7fkilrRdJ+ wioQ== X-Gm-Message-State: APjAAAWB7pIoFOrKC6W4oVJggBUI2wUP8Jac0tddgDgQac1gfBDoqqHY SrIjQ9JN1o43rA813eKX5mA= X-Google-Smtp-Source: APXvYqzb1EFsqeNTgH7vvdZ2kgpPW0N4BO6dpbRLhhgwB0krxkfOXjLwXd8MBLSAr4bTkarAvVFbiQ== X-Received: by 2002:a5d:46c9:: with SMTP id g9mr3239538wrs.211.1553188466179; Thu, 21 Mar 2019 10:14:26 -0700 (PDT) Received: from localhost (pD9E51D2D.dip0.t-ipconnect.de. [217.229.29.45]) by smtp.gmail.com with ESMTPSA id t15sm2827322wrx.22.2019.03.21.10.14.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Mar 2019 10:14:23 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 21 Mar 2019 18:14:21 +0100 Message-Id: <20190321171422.22817-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/2] ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding On Tegra210 the parents for the disp1 and disp2 clocks are slightly different from earlier chips. Only pll_p, pll_d_out0, pll_d2_out0 and clk_m are valid parents (technically pll_d_out is as well, but U-Boot doesn't know anything about it). Fix up the type name and the mux definition. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/tegra210/clock.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 06068c4b7b8d..0d7cafea2017 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -40,7 +40,7 @@ enum clock_type_id { CLOCK_TYPE_PDCT, CLOCK_TYPE_ACPT, CLOCK_TYPE_ASPTE, - CLOCK_TYPE_PMDACD2T, + CLOCK_TYPE_PDD2T, CLOCK_TYPE_PCST, CLOCK_TYPE_DP, @@ -97,8 +97,8 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), MASK_BITS_31_29}, - { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), - CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), + { CLK(PERIPH), CLK(NONE), CLK(DISPLAY), CLK(NONE), + CLK(NONE), CLK(DISPLAY2), CLK(OSC), CLK(NONE), MASK_BITS_31_29}, { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), @@ -174,8 +174,8 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), - TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), - TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), + TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDD2T), + TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDD2T), /* 0x10 */ TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),