From patchwork Tue Mar 19 15:56:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 1058514 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44NyNL2tpYz9s6w for ; Wed, 20 Mar 2019 02:56:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 15B46C21F9D; Tue, 19 Mar 2019 15:56:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7287DC21F8E; Tue, 19 Mar 2019 15:56:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5BB88C21F8E; Tue, 19 Mar 2019 15:56:41 +0000 (UTC) Received: from mx1.mailbox.org (mx1.mailbox.org [80.241.60.212]) by lists.denx.de (Postfix) with ESMTPS id E08F2C21DC1 for ; Tue, 19 Mar 2019 15:56:40 +0000 (UTC) Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mx1.mailbox.org (Postfix) with ESMTPS id BA9614C1FD; Tue, 19 Mar 2019 16:56:40 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de [80.241.56.116]) (amavisd-new, port 10030) with ESMTP id BLX_TelGyXSU; Tue, 19 Mar 2019 16:56:36 +0100 (CET) From: Stefan Roese To: u-boot@lists.denx.de Date: Tue, 19 Mar 2019 16:56:26 +0100 Message-Id: <20190319155632.5680-5-sr@denx.de> In-Reply-To: <20190319155632.5680-1-sr@denx.de> References: <20190319155632.5680-1-sr@denx.de> MIME-Version: 1.0 Subject: [U-Boot] [PATCH 05/11] watchdog: at91sam9_wdt: Fix WDT setup in at91_wdt_start() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch fixes the timer register setup in at91_wdt_start() to correctly configure the register again. The input timeout value is now in milli-seconds instead of seconds with the new watchdog API. Make sure to take this into account and only use a max timeout value of 16 seconds as appropriate for this SoC. Also the check against a lower timeout value than 0 is removed. This check makes no sense, as the timeout value is unsigned. Signed-off-by: Stefan Roese Reported-by: Heiko Schocher Cc: Heiko Schocher Cc: Andreas Bießmann Cc: Eugen Hristev --- drivers/watchdog/at91sam9_wdt.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 13f8772e41..b0a3b4ed58 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -31,27 +32,30 @@ DECLARE_GLOBAL_DATA_PTR; #define WDT_SEC2TICKS(s) (((s) << 8) - 1) /* Hardware timeout in seconds */ -#define WDT_MAX_TIMEOUT 16 -#define WDT_MIN_TIMEOUT 0 -#define WDT_DEFAULT_TIMEOUT 2 +#define WDT_MAX_TIMEOUT 16 +#define WDT_DEFAULT_TIMEOUT 2 struct at91_wdt_priv { void __iomem *regs; - u32 regval; - u32 timeout; + u32 regval; + u32 timeout; }; /* * Set the watchdog time interval in 1/256Hz (write-once) * Counter is 12 bit. */ -static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags) +static int at91_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { struct at91_wdt_priv *priv = dev_get_priv(dev); - u32 timeout = WDT_SEC2TICKS(timeout_s); + u64 timeout; + u32 ticks; - if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT) - timeout = priv->timeout; + /* Calculate timeout in seconds and the resulting ticks */ + timeout = timeout_ms; + do_div(timeout, 1000); + timeout = min_t(u64, timeout, WDT_MAX_TIMEOUT); + ticks = WDT_SEC2TICKS(timeout); /* Check if disabled */ if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) { @@ -65,12 +69,10 @@ static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags) * Since WDV is a 12-bit counter, the maximum period is * 4096 / 256 = 16 seconds. */ - priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ - | AT91_WDT_MR_WDV(timeout); /* timer value */ - + | AT91_WDT_MR_WDV(ticks); /* timer value */ writel(priv->regval, priv->regs + AT91_WDT_MR); return 0;