| Message ID | 20190306210534.9365-2-marex@denx.de |
|---|---|
| State | Accepted |
| Commit | 60082d3b3ff17fc0c5ae6c1cdd176219554ed61f |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | [U-Boot,1/4] ARM: socfpga: Disable D cache in SPL | expand |
On Wed, 2019-03-06 at 22:05 +0100, Marek Vasut wrote: > This is not used anywhere, so drop it. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Chin Liang See <chin.liang.see@intel.com> > Cc: Dinh Nguyen <dinguyen@kernel.org> > Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> > Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com> > --- > include/configs/socfpga_common.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/include/configs/socfpga_common.h > b/include/configs/socfpga_common.h > index c9cbf8f5e3..f182e9e71b 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -280,7 +280,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > > /* SPL NAND boot support */ > #ifdef CONFIG_SPL_NAND_SUPPORT > -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 > #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 > #endif >
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c9cbf8f5e3..f182e9e71b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -280,7 +280,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 #endif
This is not used anywhere, so drop it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> --- include/configs/socfpga_common.h | 1 - 1 file changed, 1 deletion(-)