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[U-Boot,U-Boot,V2,3/3] mips: fix erros on registers macros of pll-ddr-config1-nfrac for QCA956X

Message ID 20190305070434.4223-1-rosysong@rosinson.com
State Superseded
Delegated to: Daniel Schwierzeck
Headers show
Series [U-Boot,U-Boot,V2,1/3] ag7xxx: add initial support for s17 | expand

Commit Message

Rosy Song March 5, 2019, 7:04 a.m. UTC 
From: Rosy Song <rosysong@rosinson.com>

 See details in chapter 8.6.2 and 8.6.4 (page 140-141) of qca9563 datasheet,

   NFRAC[17:0]

 So the mask of [17:5] is 0x1fff not 0x3fff.

Signed-off-by: Rosy Song <rosysong@rosinson.com>
---
 arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index 7cd16b8d81..5888f6eb28 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -554,7 +554,7 @@ 
 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT		0
 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK		0x1f
 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT		5
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x3fff
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x1fff
 #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT		18
 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK		0x1ff
 
@@ -566,7 +566,7 @@ 
 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT		0
 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK		0x1f
 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT		5
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x3fff
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x1fff
 #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT		18
 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK		0x1ff