diff mbox series

[U-Boot,2/2] mv_ddr: ddr3: only use active chip-selects when tuning ODT

Message ID 20190228211114.31079-2-judge.packham@gmail.com
State Accepted
Commit 247c80d6b8ad07871845a846796ae6b40f34b4f6
Delegated to: Stefan Roese
Headers show
Series [U-Boot,1/2] mv_ddr: ddr3: fix tRAS timimg parameter | expand

Commit Message

Chris Packham Feb. 28, 2019, 9:11 p.m. UTC 
From: Chris Packham <chris.packham@alliedtelesis.co.nz>

Inactive chip-selects will give invalid values for read_sample so don't
consider them when trying to determine the overall min/max read sample.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
---
Hi Baruch,

Does this help with your boards? It's not the custom g_odt_config you
were after but it might mean that the code gets the right ODT value so
you don't have to override it.

 drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Baruch Siach March 3, 2019, 8:09 a.m. UTC | #1 
Hi Chris,

On Thu, Feb 28 2019, Chris Packham wrote:
> From: Chris Packham <chris.packham@alliedtelesis.co.nz>
>
> Inactive chip-selects will give invalid values for read_sample so don't
> consider them when trying to determine the overall min/max read sample.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>
> [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18]
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
> ---
> Hi Baruch,
>
> Does this help with your boards? It's not the custom g_odt_config you
> were after but it might mean that the code gets the right ODT value so
> you don't have to override it.

Maybe. The code looks pretty opaque to me.

Ideally we would like to have ODT_CONFIG (offset 0x1494) set to 0x30000
for all Clearfog platforms, since only ODT0 is connected. This value is
good for both 1CS and 2CS systems, although the current 0x10000 is also
fine for 1CS.

The current 2CS default hard-coded value of 0x120012 is good when both
ODT0/ODT1 are connected and both chip-selects are used. 0x30000 is not
optimal for these systems.

baruch

>  drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> index db0f8ad7fb55..df832ac6dce0 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> @@ -50,6 +50,7 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
>  	int max_phase = MIN_VALUE, current_phase;
>  	enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
>  	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
> +	unsigned int max_cs = mv_ddr_cs_num_get();
>
>  	CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
>  				       DUNIT_ODT_CTRL_REG,
> @@ -59,7 +60,7 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
>  				      data_read, MASK_ALL_BITS));
>  	val = data_read[if_id];
>
> -	for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) {
> +	for (cs_num = 0; cs_num < max_cs; cs_num++) {
>  		read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num);
>
>  		/* find maximum of read_samples */


--
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
Stefan Roese March 19, 2019, 12:39 p.m. UTC | #2 
On 28.02.19 22:11, Chris Packham wrote:
> From: Chris Packham <chris.packham@alliedtelesis.co.nz>
> 
> Inactive chip-selects will give invalid values for read_sample so don't
> consider them when trying to determine the overall min/max read sample.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> 
> [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18]
> Signed-off-by: Chris Packham <judge.packham@gmail.com>

Applied to u-boot-marvell/master.

Thanks,
Stefan
diff mbox series

Patch

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
index db0f8ad7fb55..df832ac6dce0 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
@@ -50,6 +50,7 @@  int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
 	int max_phase = MIN_VALUE, current_phase;
 	enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
 	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 
 	CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
 				       DUNIT_ODT_CTRL_REG,
@@ -59,7 +60,7 @@  int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
 				      data_read, MASK_ALL_BITS));
 	val = data_read[if_id];
 
-	for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) {
+	for (cs_num = 0; cs_num < max_cs; cs_num++) {
 		read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num);
 
 		/* find maximum of read_samples */