From patchwork Wed Feb 27 18:56:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1049107 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Mq83YaWb"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 448lRH69TKz9s1b for ; Thu, 28 Feb 2019 06:02:03 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 81C63C21DD7; Wed, 27 Feb 2019 18:59:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BE1AFC21D8E; Wed, 27 Feb 2019 18:59:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4B7B0C21DE8; Wed, 27 Feb 2019 18:58:04 +0000 (UTC) Received: from mail-pl1-f194.google.com (mail-pl1-f194.google.com [209.85.214.194]) by lists.denx.de (Postfix) with ESMTPS id 58253C21DB6 for ; Wed, 27 Feb 2019 18:58:00 +0000 (UTC) Received: by mail-pl1-f194.google.com with SMTP id b65so5416666plb.6 for ; Wed, 27 Feb 2019 10:58:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tXusBwSoAK9Li6v7yhvNgzL9e03cMXp3MHygui5bFzk=; b=Mq83YaWbbii2tkw04ED1B2aycvgN1mb1omBId7UADwtFlGLC7rTIMEqSUmT/wBhmkv VmqYdn2eGNpNy2cggRm4ffrnjJ3o2S1RUrzHUyYVgzhU3R4eWnD1yDkpgV0/z6dHRGG8 G+Y+ZH2d1YAxKQE6GSdRrFy/YRGwul2v9PkU8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tXusBwSoAK9Li6v7yhvNgzL9e03cMXp3MHygui5bFzk=; b=T5CANvqjYwtKxJnjoLURiqn6DzyJIcfSIEht58Ihr6QK6zeBCozEQ9/Avmw2MBpmle arL0wf+PMxv7xVLh7CtWUKZUzqkeMYAnkbI6JJUVt2aSM/WgA8hfVhluV1/YuE5a2Kli sTY24scsEGRgLw7S7f5m9dYPKiyOrH3Fe+8Pil8wU6Tgvy/OPF9PI4r74AA36dYyrx9D qS8LjHP9GiQ3Z7VIfvo7+ImTNQA8kOlN68LLlkdDLyGuipjhQWk4NKo62Sv/APGeyCz3 E3Uu9wvG4mNwm6Ucv8Vyj8rC4XQEsZvZ6Uwa1X0fCxNO7RrDYIV6cLGfatLv8irmhR/3 ZiXw== X-Gm-Message-State: AHQUAuYoac2H3TyNIwshuZF/K3/vtc9circOcC8jbp2sVgQ/9Mj9B/A5 ciIsG2x+QsyxsSuP8JLBO/lY/w== X-Google-Smtp-Source: AHgI3IblCTS/UlmpNgIxTqy1NA6tvbCE6CP548GBfUxGk4TXbfu20MluTYwO1TX+HVhH2yWeUkdYRA== X-Received: by 2002:a17:902:b58c:: with SMTP id a12mr3709709pls.102.1551293878967; Wed, 27 Feb 2019 10:57:58 -0800 (PST) Received: from localhost.localdomain ([115.97.184.151]) by smtp.gmail.com with ESMTPSA id z6sm22020802pgo.31.2019.02.27.10.57.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Feb 2019 10:57:58 -0800 (PST) From: Jagan Teki To: =?utf-8?q?Andr=C3=A9_Przywara?= , Maxime Ripard , Chen-Yu Tsai Date: Thu, 28 Feb 2019 00:26:58 +0530 Message-Id: <20190227185701.15545-11-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190227185701.15545-1-jagan@amarulasolutions.com> References: <20190227185701.15545-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Lothar Felten , Joe Hershberger Subject: [U-Boot] [PATCH v3 10/13] net: sun8i_emac: Add CLK and RESET support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger Cc: Lothar Felten Signed-off-by: Jagan Teki Acked-by: Joe Hershberger --- drivers/net/sun8i_emac.c | 57 +++++++++++++++++++++++++++++----------- 1 file changed, 42 insertions(+), 15 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index a7fb7ac405..98bd7a5823 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -14,12 +14,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #ifdef CONFIG_DM_GPIO #include @@ -135,6 +137,8 @@ struct emac_eth_dev { phys_addr_t sysctl_reg; struct phy_device *phydev; struct mii_dev *bus; + struct clk tx_clk; + struct reset_ctl tx_rst; #ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; #endif @@ -647,9 +651,24 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev) return _sun8i_write_hwaddr(priv, pdata->enetaddr); } -static void sun8i_emac_board_setup(struct emac_eth_dev *priv) +static int sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int ret; + + ret = clk_enable(&priv->tx_clk); + if (ret) { + dev_err(dev, "failed to enable TX clock\n"); + return ret; + } + + if (reset_valid(&priv->tx_rst)) { + ret = reset_deassert(&priv->tx_rst); + if (ret) { + dev_err(dev, "failed to deassert TX reset\n"); + goto err_tx_clk; + } + } if (priv->variant == H3_EMAC) { /* Only H3/H5 have clock controls for internal EPHY */ @@ -664,19 +683,11 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) } } - if (priv->variant == R40_GMAC) { - /* Set clock gating for emac */ - setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC)); - - /* De-assert EMAC */ - setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC)); - } else { - /* Set clock gating for emac */ - setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); + return 0; - /* De-assert EMAC */ - setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); - } +err_tx_clk: + clk_disable(&priv->tx_clk); + return ret; } #if defined(CONFIG_DM_GPIO) @@ -803,10 +814,14 @@ static int sun8i_emac_eth_probe(struct udevice *dev) struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; struct emac_eth_dev *priv = dev_get_priv(dev); + int ret; priv->mac_reg = (void *)pdata->iobase; - sun8i_emac_board_setup(priv); + ret = sun8i_emac_board_setup(priv); + if (ret) + return ret; + sun8i_emac_set_syscon(sun8i_pdata, priv); sun8i_mdio_init(dev->name, dev); @@ -835,8 +850,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) int offset = 0; #ifdef CONFIG_DM_GPIO int reset_flags = GPIOD_IS_OUT; - int ret = 0; #endif + int ret; pdata->iobase = devfdt_get_addr(dev); if (pdata->iobase == FDT_ADDR_T_NONE) { @@ -851,6 +866,18 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } + ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk); + if (ret) { + dev_err(dev, "failed to get TX clock\n"); + return ret; + } + + ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get TX reset\n"); + return ret; + } + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); if (offset < 0) { debug("%s: cannot find syscon node\n", __func__);