From patchwork Thu Feb 21 22:35:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 1046487 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="tpxelpgF"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4458TR5hdjz9s6w for ; Fri, 22 Feb 2019 09:36:27 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7461BC21E4F; Thu, 21 Feb 2019 22:36:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 75FB2C21E6C; Thu, 21 Feb 2019 22:35:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A9AACC21E02; Thu, 21 Feb 2019 22:35:20 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lists.denx.de (Postfix) with ESMTPS id 65ED5C21C4A for ; Thu, 21 Feb 2019 22:35:19 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1LMZFwJ084189; Thu, 21 Feb 2019 16:35:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1550788515; bh=d02RsfGUOECSMaNx+z35BTi4fKrpSgell8ixbZjPgeY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tpxelpgFKGsjJd7KPzb6XoR69o2a5nm8sGHBHMJVrc70Xq7Yw84AKP4RDU9AFsfDl QfBylub1n9LJIEjgAF0Ba7ycqeO6PXc+iGNU4N4SzFL3VWA06tfrvSFQiTM82pa3FV QKUOvGqtgI3o9q7QF8W4f6MMmSKtth+6L5Bhh6j8= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1LMZFPN032293 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 21 Feb 2019 16:35:15 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 21 Feb 2019 16:35:15 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 21 Feb 2019 16:35:15 -0600 Received: from legion.dal.desgin.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1LMZF9i027221; Thu, 21 Feb 2019 16:35:15 -0600 Received: from localhost (uda0226330.dhcp.ti.com [172.22.111.174]) by legion.dal.desgin.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x1LMZEU08561; Thu, 21 Feb 2019 16:35:14 -0600 (CST) From: "Andrew F. Davis" To: Tom Rini , Lokesh Vutla , Andreas Dannenberg Date: Thu, 21 Feb 2019 16:35:06 -0600 Message-ID: <20190221223512.8310-2-afd@ti.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190221223512.8310-1-afd@ti.com> References: <20190221223512.8310-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 1/7] arm: K3: Avoid use of MCU_PSRAM0 before SYSFW is loaded X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" On HS devices the 512b region of reset isolated memory called MCU_PSRAM0 is firewalled by default. Until SYSFW is loaded we cannot use this memory. It is only used to store a single value left at the end of SRAM by ROM that will be needed later. Save that value to a global variable stored in the .data section. This section is used as .bss will be cleared between saving this value and using it. Signed-off-by: Andrew F. Davis Reviewed-by: Andreas Dannenberg Reviewed-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/mach-k3/am6_init.c | 13 ++++++++----- arch/arm/mach-k3/include/mach/am6_hardware.h | 3 --- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index a5553190b4..2301061848 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -49,11 +49,16 @@ static void ctrl_mmr_unlock(void) mmr_unlock(CTRL_MMR0_BASE, 7); } +/* + * This uninitialized global variable would normal end up in the .bss section, + * but the .bss is cleared between writing and reading this variable, so move + * it to the .data section. + */ +u32 bootindex __attribute__((section(".data"))); + static void store_boot_index_from_rom(void) { - u32 *boot_index = (u32 *)K3_BOOT_PARAM_TABLE_INDEX_VAL; - - *boot_index = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); } void board_init_f(ulong dummy) @@ -94,7 +99,6 @@ u32 spl_boot_mode(const u32 boot_device) { #if defined(CONFIG_SUPPORT_EMMC_BOOT) u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); - u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL); u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >> CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT; @@ -170,7 +174,6 @@ static u32 __get_primary_bootmedia(u32 devstat) u32 spl_boot_device(void) { u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); - u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL); if (bootindex == K3_PRIMARY_BOOTMODE) return __get_primary_bootmedia(devstat); diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index b5244609af..3343233aa3 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -44,7 +44,4 @@ #define CTRLMMR_LOCK_KICK1 0x0100c #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a -/* MCU SCRATCHPAD usage */ -#define K3_BOOT_PARAM_TABLE_INDEX_VAL CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE - #endif /* __ASM_ARCH_AM6_HARDWARE_H */