From patchwork Mon Feb 18 16:28:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 1044164 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="AbO48dK1"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4438Q40TwZz9s3l for ; Tue, 19 Feb 2019 03:26:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B1E7EC21F98; Mon, 18 Feb 2019 16:26:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 520F8C21F98; Mon, 18 Feb 2019 16:26:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 89B76C21F6E; Mon, 18 Feb 2019 16:26:01 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id D6ADFC21F4D for ; Mon, 18 Feb 2019 16:26:00 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1IGPvGC092462; Mon, 18 Feb 2019 10:25:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1550507157; bh=jjI8x7WApSf09/dHSgWY7iWb1KmM7KJigsSDIvHgcfg=; h=From:To:Subject:Date:In-Reply-To:References; b=AbO48dK1ttRp3rMB/ilqU9iq8jk9b3Izu25NJdXnAOcGSMXZScjwYMY5xUMEolE2q VZjVD/BMMqaEE7+XjBk/xWYx5DAe4VWWjusu0DP4hVqlbpV4DTH6xYzHBMNXSoTyUV PiITCEwoOJnPQr6fk2Zah1kA0yyXNlg2ccFWxXqo= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1IGPvsj092439 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 18 Feb 2019 10:25:57 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 18 Feb 2019 10:25:56 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 18 Feb 2019 10:25:56 -0600 Received: from uda0868495.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1IGPrQD024271; Mon, 18 Feb 2019 10:25:56 -0600 From: Murali Karicheri To: , , , , , , , Date: Mon, 18 Feb 2019 11:28:01 -0500 Message-ID: <20190218162804.26470-5-m-karicheri2@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20190218162804.26470-1-m-karicheri2@ti.com> References: <20190218162804.26470-1-m-karicheri2@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Subject: [U-Boot] [PATCH v2 4/7] ARM: k2g: add a workaround to reset the phy X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds a workaround to reset the phy one time during boot using GPIO0 pin 10 to make sure, the Phy latches the configuration from the input pins correctly. Signed-off-by: Murali Karicheri --- .../arm/mach-keystone/include/mach/hardware-k2g.h | 3 +++ board/ti/ks2_evm/board_k2g.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h index 8b902641ec..971c081bb3 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -69,9 +69,12 @@ #define K2G_GPIO0_BASE 0X02603000 #define K2G_GPIO1_BASE 0X0260a000 +#define K2G_GPIO0_BANK0_BASE K2G_GPIO0_BASE + 0x10 #define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38 #define K2G_GPIO_DIR_OFFSET 0x0 +#define K2G_GPIO_OUTDATA_OFFSET 0x4 #define K2G_GPIO_SETDATA_OFFSET 0x8 +#define K2G_GPIO_CLRDATA_OFFSET 0xC /* BOOTCFG RESETMUX8 */ #define KS2_RSTMUX8 (KS2_DEVICE_STATE_CTRL_BASE + 0x328) diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 39a782e479..6d0fc21c67 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -315,6 +315,21 @@ int embedded_dtb_select(void) BIT(9)); setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, BIT(9)); + } else if (board_is_k2g_ice()) { + /* GBE Phy workaround. For Phy to latch the input + * configuration, a GPIO reset is asserted at the + * Phy reset pin to latch configuration correctly after SoC + * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE + * board. Just do a low to high transition. + */ + clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET, + BIT(10)); + setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET, + BIT(10)); + /* Delay just to get a transition to high */ + udelay(100); + setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET, + BIT(10)); } return 0;