diff mbox series

[U-Boot,4/4] arm: mvebu: Add DB-XC3-24G4XG board

Message ID 20190215094137.1933-5-judge.packham@gmail.com
State Superseded
Delegated to: Stefan Roese
Headers show
Series Marvell DB-XC3-24G4XG board support | expand

Commit Message

Chris Packham Feb. 15, 2019, 9:41 a.m. UTC 
From: Chris Packham <chris.packham@alliedtelesis.co.nz>

The DB-XC3-24G4XG is a switch development board from Marvell. It can
either use and external CPU card such as the db-88f6820-amc or the
internal CPU that is integrated into the switch.

Add support for running U-Boot on the internal CPU and enable the USB,
SPI and NAND peripherals. For now this needs the bin_hdr from the
Marvell U-Boot for this board.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
---

 arch/arm/dts/Makefile                       |   3 +-
 arch/arm/dts/armada-xp-98dx3236.dtsi        | 343 ++++++++++++++++++++
 arch/arm/dts/armada-xp-98dx3336.dtsi        |  39 +++
 arch/arm/dts/armada-xp-98dx4251.dtsi        |  54 +++
 arch/arm/dts/armada-xp-db-xc3-24g4xg.dts    | 122 +++++++
 arch/arm/mach-mvebu/Kconfig                 |   8 +
 board/Marvell/db-xc3-24g4xg/MAINTAINERS     |   7 +
 board/Marvell/db-xc3-24g4xg/Makefile        |   5 +
 board/Marvell/db-xc3-24g4xg/README          |   4 +
 board/Marvell/db-xc3-24g4xg/binary.0        |  11 +
 board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c |  71 ++++
 board/Marvell/db-xc3-24g4xg/kwbimage.cfg    |  12 +
 configs/db-xc3-24g4xg_defconfig             |  55 ++++
 include/configs/db-xc3-24g4xg.h             |  45 +++
 tools/Makefile                              |   4 +
 tools/kwbimage.c                            |   4 +
 16 files changed, 786 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/armada-xp-98dx3236.dtsi
 create mode 100644 arch/arm/dts/armada-xp-98dx3336.dtsi
 create mode 100644 arch/arm/dts/armada-xp-98dx4251.dtsi
 create mode 100644 arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
 create mode 100644 board/Marvell/db-xc3-24g4xg/MAINTAINERS
 create mode 100644 board/Marvell/db-xc3-24g4xg/Makefile
 create mode 100644 board/Marvell/db-xc3-24g4xg/README
 create mode 100644 board/Marvell/db-xc3-24g4xg/binary.0
 create mode 100644 board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
 create mode 100644 board/Marvell/db-xc3-24g4xg/kwbimage.cfg
 create mode 100644 configs/db-xc3-24g4xg_defconfig
 create mode 100644 include/configs/db-xc3-24g4xg.h

Comments

Stefan Roese Feb. 15, 2019, 10:17 a.m. UTC | #1 
Hi Chris,

please find a few comments / questions below.

On 15.02.19 10:41, Chris Packham wrote:
> From: Chris Packham <chris.packham@alliedtelesis.co.nz>
> 
> The DB-XC3-24G4XG is a switch development board from Marvell. It can
> either use and external CPU card such as the db-88f6820-amc or the
> internal CPU that is integrated into the switch.
> 
> Add support for running U-Boot on the internal CPU and enable the USB,
> SPI and NAND peripherals. For now this needs the bin_hdr from the
> Marvell U-Boot for this board.
> 
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
> ---
> 
>   arch/arm/dts/Makefile                       |   3 +-
>   arch/arm/dts/armada-xp-98dx3236.dtsi        | 343 ++++++++++++++++++++
>   arch/arm/dts/armada-xp-98dx3336.dtsi        |  39 +++
>   arch/arm/dts/armada-xp-98dx4251.dtsi        |  54 +++
>   arch/arm/dts/armada-xp-db-xc3-24g4xg.dts    | 122 +++++++
>   arch/arm/mach-mvebu/Kconfig                 |   8 +
>   board/Marvell/db-xc3-24g4xg/MAINTAINERS     |   7 +
>   board/Marvell/db-xc3-24g4xg/Makefile        |   5 +
>   board/Marvell/db-xc3-24g4xg/README          |   4 +
>   board/Marvell/db-xc3-24g4xg/binary.0        |  11 +
>   board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c |  71 ++++
>   board/Marvell/db-xc3-24g4xg/kwbimage.cfg    |  12 +
>   configs/db-xc3-24g4xg_defconfig             |  55 ++++
>   include/configs/db-xc3-24g4xg.h             |  45 +++
>   tools/Makefile                              |   4 +
>   tools/kwbimage.c                            |   4 +

Could you please split the kwbimage tool changes into a separate
patch?

>   16 files changed, 786 insertions(+), 1 deletion(-)
>   create mode 100644 arch/arm/dts/armada-xp-98dx3236.dtsi
>   create mode 100644 arch/arm/dts/armada-xp-98dx3336.dtsi
>   create mode 100644 arch/arm/dts/armada-xp-98dx4251.dtsi
>   create mode 100644 arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
>   create mode 100644 board/Marvell/db-xc3-24g4xg/MAINTAINERS
>   create mode 100644 board/Marvell/db-xc3-24g4xg/Makefile
>   create mode 100644 board/Marvell/db-xc3-24g4xg/README
>   create mode 100644 board/Marvell/db-xc3-24g4xg/binary.0
>   create mode 100644 board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
>   create mode 100644 board/Marvell/db-xc3-24g4xg/kwbimage.cfg
>   create mode 100644 configs/db-xc3-24g4xg_defconfig
>   create mode 100644 include/configs/db-xc3-24g4xg.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ca5062348087..133f09d8ba63 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -113,7 +113,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
>   	armada-xp-theadorable.dtb		\
>   	armada-38x-controlcenterdc.dtb		\
>   	armada-385-atl-x530.dtb			\
> -	armada-385-atl-x530DP.dtb
> +	armada-385-atl-x530DP.dtb		\
> +	armada-xp-db-xc3-24g4xg.dtb
>   
>   dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
>   	uniphier-ld11-global.dtb \
> diff --git a/arch/arm/dts/armada-xp-98dx3236.dtsi b/arch/arm/dts/armada-xp-98dx3236.dtsi
> new file mode 100644
> index 000000000000..5df1d1848dbc
> --- /dev/null
> +++ b/arch/arm/dts/armada-xp-98dx3236.dtsi
> @@ -0,0 +1,343 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree Include file for Marvell 98dx3236 family SoC
> + *
> + * Copyright (C) 2016 Allied Telesis Labs
> + *
> + * Contains definitions specific to the 98dx3236 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> +#include "armada-370-xp.dtsi"
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	model = "Marvell 98DX3236 SoC";
> +	compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> +
> +	aliases {
> +		gpio0 = &gpio0;
> +		gpio1 = &gpio1;
> +		gpio2 = &gpio2;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		enable-method = "marvell,98dx3236-smp";
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "marvell,sheeva-v7";
> +			reg = <0>;
> +			clocks = <&cpuclk 0>;
> +			clock-latency = <1000000>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "marvell,armadaxp-mbus", "simple-bus";
> +
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> +			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> +			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> +			  MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> +			  MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> +
> +		bootrom {
> +			compatible = "marvell,bootrom";
> +			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
> +		};
> +
> +		/*
> +		 * 98DX3236 has 1 x1 PCIe unit Gen2.0
> +		 */
> +		pciec: pcie@82000000 {
> +			compatible = "marvell,armada-xp-pcie";
> +			status = "disabled";
> +			device_type = "pci";
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +
> +			msi-parent = <&mpic>;
> +			bus-range = <0x00 0xff>;
> +
> +			ranges =
> +			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
> +				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
> +				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */>;
> +
> +			pcie1: pcie@1,0 {
> +				device_type = "pci";
> +				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
> +				reg = <0x0800 0 0 0 0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
> +					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
> +				bus-range = <0x00 0xff>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &mpic 58>;
> +				marvell,pcie-port = <0>;
> +				marvell,pcie-lane = <0>;
> +				clocks = <&gateclk 5>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		internal-regs {
> +			sdramc: sdramc@1400 {
> +				compatible = "marvell,armada-xp-sdram-controller";
> +				reg = <0x1400 0x500>;
> +			};
> +
> +			L2: l2-cache@8000 {
> +				compatible = "marvell,aurora-system-cache";
> +				reg = <0x08000 0x1000>;
> +				cache-id-part = <0x100>;
> +				cache-level = <2>;
> +				cache-unified;
> +				wt-override;
> +			};
> +
> +			gpio0: gpio@18100 {
> +				compatible = "marvell,orion-gpio";
> +				reg = <0x18100 0x40>;
> +				ngpios = <32>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <82>, <83>, <84>, <85>;
> +			};
> +
> +			/* does not exist */
> +			gpio1: gpio@18140 {
> +				compatible = "marvell,orion-gpio";
> +				reg = <0x18140 0x40>;
> +				status = "disabled";
> +			};
> +
> +			gpio2: gpio@18180 { /* rework some properties */
> +				compatible = "marvell,orion-gpio";
> +				reg = <0x18180 0x40>;
> +				ngpios = <1>; /* only gpio #32 */
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <87>;
> +			};
> +
> +			systemc: system-controller@18200 {
> +				compatible = "marvell,armada-370-xp-system-controller";
> +				reg = <0x18200 0x500>;
> +			};
> +
> +			gateclk: clock-gating-control@18220 {
> +				compatible = "marvell,mv98dx3236-gating-clock";
> +				reg = <0x18220 0x4>;
> +				clocks = <&coreclk 0>;
> +				#clock-cells = <1>;
> +			};
> +
> +			cpuclk: clock-complex@18700 {
> +				#clock-cells = <1>;
> +				compatible = "marvell,mv98dx3236-cpu-clock";
> +				reg = <0x18700 0x24>, <0x1c054 0x10>;
> +				clocks = <&coreclk 1>;
> +			};
> +
> +			corediv-clock@18740 {
> +				status = "disabled";
> +			};
> +
> +			cpu-config@21000 {
> +				compatible = "marvell,armada-xp-cpu-config";
> +				reg = <0x21000 0x8>;
> +			};
> +
> +			ethernet@70000 {
> +				compatible = "marvell,armada-xp-neta";
> +			};
> +
> +			ethernet@74000 {
> +				compatible = "marvell,armada-xp-neta";
> +			};
> +
> +			xor1: xor@f0800 {
> +				compatible = "marvell,orion-xor";
> +				reg = <0xf0800 0x100
> +				       0xf0a00 0x100>;
> +				clocks = <&gateclk 22>;
> +				status = "okay";
> +
> +				xor10 {
> +					interrupts = <51>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +				};
> +				xor11 {
> +					interrupts = <52>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +					dmacap,memset;
> +				};
> +			};
> +
> +			nand_controller: nand@d0000 {
> +				clocks = <&dfx_coredivclk 0>;
> +			};
> +
> +			xor0: xor@f0900 {
> +				compatible = "marvell,orion-xor";
> +				reg = <0xF0900 0x100
> +				       0xF0B00 0x100>;
> +				clocks = <&gateclk 28>;
> +				status = "okay";
> +
> +				xor00 {
> +					interrupts = <94>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +				};
> +				xor01 {
> +					interrupts = <95>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +					dmacap,memset;
> +				};
> +			};
> +		};
> +
> +		dfx: dfx-server@ac000000 {
> +			compatible = "marvell,dfx-server", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
> +			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
> +
> +                        thermal: thermal@f8078 {
> +                                compatible = "marvell,armada380-thermal";
> +                                reg = <0xf8078 0x4>, <0xf8074 0x4>;
> +                                status = "okay";
> +                        };
> +
> +			coreclk: mvebu-sar@f8204 {
> +				compatible = "marvell,mv98dx3236-core-clock";
> +				reg = <0xf8204 0x4>;
> +				#clock-cells = <1>;
> +			};
> +
> +			dfx_coredivclk: corediv-clock@f8268 {
> +				compatible = "marvell,mv98dx3236-corediv-clock";
> +				reg = <0xf8268 0xc>;
> +				#clock-cells = <1>;
> +				clocks = <&mainpll>;
> +				clock-output-names = "nand";
> +			};
> +		};
> +
> +		switch: switch@a8000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
> +
> +			pp0: packet-processor@0 {
> +				compatible = "marvell,prestera-98dx3236", "marvell,prestera";
> +				reg = <0 0x4000000>;
> +				interrupts = <33>, <34>, <35>;
> +				dfx = <&dfx>;
> +			};
> +		};
> +	};
> +
> +	clocks {
> +		/* 25 MHz reference crystal */
> +		refclk: oscillator {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <25000000>;
> +		};
> +	};
> +};
> +
> +&i2c0 {
> +	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
> +	reg = <0x11000 0x100>;
> +};
> +
> +&i2c1 {
> +	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
> +	reg = <0x11100 0x100>;
> +};
> +
> +&mpic {
> +	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
> +};
> +
> +&rtc {
> +	status = "disabled";
> +};
> +
> +&timer {
> +	compatible = "marvell,armada-xp-timer";
> +	clocks = <&coreclk 2>, <&refclk>;
> +	clock-names = "nbclk", "fixed";
> +};
> +
> +&watchdog {
> +	compatible = "marvell,armada-xp-wdt";
> +	clocks = <&coreclk 2>, <&refclk>;
> +	clock-names = "nbclk", "fixed";
> +};
> +
> +&cpurst {
> +	reg = <0x20800 0x20>;
> +};
> +
> +&usb0 {
> +	clocks = <&gateclk 18>;
> +};
> +
> +&usb1 {
> +	clocks = <&gateclk 19>;
> +};
> +
> +&pinctrl {
> +	compatible = "marvell,98dx3236-pinctrl";
> +
> +	nand_pins: nand-pins {
> +		marvell,pins = "mpp20", "mpp21", "mpp22",
> +			       "mpp23", "mpp24", "mpp25",
> +			       "mpp26", "mpp27", "mpp28",
> +			       "mpp29", "mpp30";
> +		marvell,function = "dev";
> +	};
> +
> +	nand_rb: nand-rb {
> +		marvell,pins = "mpp19";
> +		marvell,function = "nand";
> +	};
> +
> +	spi0_pins: spi0-pins {
> +		marvell,pins = "mpp0", "mpp1",
> +			       "mpp2", "mpp3";
> +		marvell,function = "spi0";
> +	};
> +};
> +
> +&spi0 {
> +	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
> +	pinctrl-0 = <&spi0_pins>;
> +	pinctrl-names = "default";
> +};
> +
> +&sdio {
> +	status = "disabled";
> +};
> diff --git a/arch/arm/dts/armada-xp-98dx3336.dtsi b/arch/arm/dts/armada-xp-98dx3336.dtsi
> new file mode 100644
> index 000000000000..1d9d8a8ea60c
> --- /dev/null
> +++ b/arch/arm/dts/armada-xp-98dx3336.dtsi
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree Include file for Marvell 98dx3336 family SoC
> + *
> + * Copyright (C) 2016 Allied Telesis Labs
> + *
> + * Contains definitions specific to the 98dx3236 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> +#include "armada-xp-98dx3236.dtsi"
> +
> +/ {
> +	model = "Marvell 98DX3336 SoC";
> +	compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> +
> +	cpus {
> +		cpu@1 {
> +			device_type = "cpu";
> +			compatible = "marvell,sheeva-v7";
> +			reg = <1>;
> +			clocks = <&cpuclk 1>;
> +			clock-latency = <1000000>;
> +		};
> +	};
> +
> +	soc {
> +		internal-regs {
> +			resume@20980 {
> +				compatible = "marvell,98dx3336-resume-ctrl";
> +				reg = <0x20980 0x10>;
> +			};
> +		};
> +	};
> +};
> +
> +&pp0 {
> +	compatible = "marvell,prestera-98dx3336", "marvell,prestera";
> +};
> diff --git a/arch/arm/dts/armada-xp-98dx4251.dtsi b/arch/arm/dts/armada-xp-98dx4251.dtsi
> new file mode 100644
> index 000000000000..48ffdc72bfc7
> --- /dev/null
> +++ b/arch/arm/dts/armada-xp-98dx4251.dtsi
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree Include file for Marvell 98dx4521 family SoC
> + *
> + * Copyright (C) 2016 Allied Telesis Labs
> + *
> + * Contains definitions specific to the 98dx4521 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> +#include "armada-xp-98dx3236.dtsi"
> +
> +/ {
> +	model = "Marvell 98DX4251 SoC";
> +	compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> +
> +	cpus {
> +		cpu@1 {
> +			device_type = "cpu";
> +			compatible = "marvell,sheeva-v7";
> +			reg = <1>;
> +			clocks = <&cpuclk 1>;
> +			clock-latency = <1000000>;
> +		};
> +	};
> +
> +	soc {
> +		internal-regs {
> +			resume@20980 {
> +				compatible = "marvell,98dx3336-resume-ctrl";
> +				reg = <0x20980 0x10>;
> +			};
> +		};
> +	};
> +};
> +
> +&sdio {
> +	status = "okay";
> +};
> +
> +&pinctrl {
> +	compatible = "marvell,98dx4251-pinctrl";
> +
> +	sdio_pins: sdio-pins {
> +		marvell,pins = "mpp5", "mpp6", "mpp7",
> +			       "mpp8", "mpp9", "mpp10";
> +		marvell,function = "sd0";
> +	};
> +};
> +
> +&pp0 {
> +	compatible = "marvell,prestera-98dx4251", "marvell,prestera";
> +	interrupts = <33>, <34>, <35>, <36>;
> +};
> diff --git a/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> new file mode 100644
> index 000000000000..2daf83e655ac
> --- /dev/null
> +++ b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for DB-XC3-24G4XG board
> + *
> + * Copyright (C) 2016 Allied Telesis Labs
> + *
> + * Based on armada-xp-db.dts
> + *
> + * Note: this Device Tree assumes that the bootloader has remapped the
> + * internal registers to 0xf1000000 (instead of the default
> + * 0xd0000000). The 0xf1000000 is the default used by the recent,
> + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
> + * boards were delivered with an older version of the bootloader that
> + * left internal registers mapped at 0xd0000000. If you are in this
> + * situation, you should either update your bootloader (preferred
> + * solution) or the below Device Tree should be adjusted.
> + */
> +
> +/dts-v1/;
> +#include "armada-xp-98dx3336.dtsi"
> +
> +/ {
> +	model = "DB-XC3-24G4XG";
> +	compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +		bootargs = "console=ttyS0,115200 earlyprintk";
> +	};
> +
> +	aliases {
> +		spi0 = &spi0;
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
> +	};
> +};
> +
> +&L2 {
> +	arm,parity-enable;
> +	marvell,ecc-enable;
> +};
> +
> +&devbus_bootcs {
> +	status = "okay";
> +
> +	/* Device Bus parameters are required */
> +
> +	/* Read parameters */
> +	devbus,bus-width    = <16>;
> +	devbus,turn-off-ps  = <60000>;
> +	devbus,badr-skew-ps = <0>;
> +	devbus,acc-first-ps = <124000>;
> +	devbus,acc-next-ps  = <248000>;
> +	devbus,rd-setup-ps  = <0>;
> +	devbus,rd-hold-ps   = <0>;
> +
> +	/* Write parameters */
> +	devbus,sync-enable = <0>;
> +	devbus,wr-high-ps  = <60000>;
> +	devbus,wr-low-ps   = <60000>;
> +	devbus,ale-wr-ps   = <60000>;
> +};
> +
> +&uart0 {
> +	status = "okay";
> +	u-boot,dm-pre-reloc;

All U-Boot specific DT properties into a *-u-boot.dtsi file please.

> +};
> +
> +&uart1 {
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	clock-frequency = <100000>;
> +	status = "okay";
> +};
> +
> +&nand_controller {
> +	compatible="marvell,mvebu-pxa3xx-nand";
> +	status = "okay";
> +	label = "pxa3xx_nand-0";
> +	nand-rb = <0>;
> +	marvell,nand-keep-config;
> +	nand-on-flash-bbt;
> +	nand-ecc-strength = <4>;
> +	nand-ecc-step-size = <512>;
> +};
> +
> +&usb0 {
> +	status = "okay";
> +};
> +
> +&spi0 {
> +	status = "okay";
> +	u-boot,dm-pre-reloc;

Here as well and all other occurrences too please.

> +
> +	spi-flash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "spi-flash", "jedec,spi-nor";
> +		reg = <0>; /* Chip select 0 */
> +		spi-max-frequency = <108000000>;
> +		m25p,fast-read;
> +
> +		partition@u-boot {
> +			reg = <0x00000000 0x00100000>;
> +			label = "u-boot";
> +		};
> +		partition@u-boot-env {
> +			reg = <0x00100000 0x00040000>;
> +			label = "u-boot-env";
> +		};
> +		partition@unused {
> +			reg = <0x00140000 0x00ec0000>;
> +			label = "unused";
> +		};
> +
> +	};
> +};
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 05aa2ade0499..938466615c66 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -152,6 +152,10 @@ config TARGET_X530
>   	bool "Support Allied Telesis x530"
>   	select 88F6820
>   
> +config TARGET_DB_XC3_24G4XG
> +	bool "Support DB-XC3-24G4XG"
> +	select 98DX3336
> +
>   endchoice
>   
>   config SYS_BOARD
> @@ -170,6 +174,7 @@ config SYS_BOARD
>   	default "theadorable" if TARGET_THEADORABLE
>   	default "a38x" if TARGET_CONTROLCENTERDC
>   	default "x530" if TARGET_X530
> +	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
>   
>   config SYS_CONFIG_NAME
>   	default "clearfog" if TARGET_CLEARFOG
> @@ -187,6 +192,7 @@ config SYS_CONFIG_NAME
>   	default "turris_mox" if TARGET_TURRIS_MOX
>   	default "controlcenterdc" if TARGET_CONTROLCENTERDC
>   	default "x530" if TARGET_X530
> +	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
>   
>   config SYS_VENDOR
>   	default "Marvell" if TARGET_DB_MV784MP_GP
> @@ -195,6 +201,8 @@ config SYS_VENDOR
>   	default "Marvell" if TARGET_DB_88F6820_GP
>   	default "Marvell" if TARGET_DB_88F6820_AMC
>   	default "Marvell" if TARGET_MVEBU_ARMADA_8K
> +	default "Marvell" if TARGET_DB_XC3_24G4XG
> +	default "Marvell" if TARGET_MVEBU_DB_88F7040
>   	default "solidrun" if TARGET_CLEARFOG
>   	default "kobol" if TARGET_HELIOS4
>   	default "Synology" if TARGET_DS414
> diff --git a/board/Marvell/db-xc3-24g4xg/MAINTAINERS b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
> new file mode 100644
> index 000000000000..94d4a901783b
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
> @@ -0,0 +1,7 @@
> +DB-XC3-24G4XG BOARD
> +M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
> +S:	Maintained
> +F:	board/Marvell/db-xc3-24g4xg/
> +F:	include/configs/db-xc3-24g4xg.h
> +F:	configs/db-xc3-24g4xg-amc_defconfig
> +F:	arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> diff --git a/board/Marvell/db-xc3-24g4xg/Makefile b/board/Marvell/db-xc3-24g4xg/Makefile
> new file mode 100644
> index 000000000000..199837a84fe6
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2015 Stefan Roese <sr@denx.de>
> +
> +obj-y	:= db-xc3-24g4xg.o
> diff --git a/board/Marvell/db-xc3-24g4xg/README b/board/Marvell/db-xc3-24g4xg/README
> new file mode 100644
> index 000000000000..5e479b433e4d
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/README
> @@ -0,0 +1,4 @@
> +To generate binary.0 from Marvell's bin_hdr.elf use the following command
> +
> +    arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \
> +       board/Marvell/db-xc3-24g4xg/binary.0
> diff --git a/board/Marvell/db-xc3-24g4xg/binary.0 b/board/Marvell/db-xc3-24g4xg/binary.0
> new file mode 100644
> index 000000000000..8dd687286a00
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/binary.0
> @@ -0,0 +1,11 @@
> +--------
> +WARNING:
> +--------
> +This file should contain the bin_hdr generated by the original Marvell
> +U-Boot implementation. As this is currently not included in this
> +U-Boot version, we have added this placeholder, so that the U-Boot
> +image can be generated without errors.
> +
> +If you have a known to be working bin_hdr for your board, then you
> +just need to replace this text file here with the binary header
> +and recompile U-Boot.
> diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> new file mode 100644
> index 000000000000..428e3f611798
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2015 Stefan Roese <sr@denx.de>
> + */
> +
> +#include <common.h>
> +#include <i2c.h>
> +#include <asm/gpio.h>
> +#include <linux/mbus.h>
> +#include <linux/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/soc.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * These values and defines are taken from the Marvell U-Boot version
> + * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
> + */
> +#define DB_DX_AC3_GPP_OUT_ENA_LOW	(~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
> +					| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29)  | BIT(30)))
> +#define DB_DX_AC3_GPP_OUT_ENA_MID	(~(0))
> +#define DB_DX_AC3_GPP_OUT_VAL_LOW	(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
> +					| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29)  | BIT(30))
> +#define DB_DX_AC3_GPP_OUT_VAL_MID	0x0
> +#define DB_DX_AC3_GPP_POL_LOW		0x0
> +#define DB_DX_AC3_GPP_POL_MID		0x0
> +
> +int board_early_init_f(void)
> +{
> +	/* Configure MPP */
> +	writel(0x00142222, MVEBU_MPP_BASE + 0x00);
> +	writel(0x11122000, MVEBU_MPP_BASE + 0x04);
> +	writel(0x44444004, MVEBU_MPP_BASE + 0x08);
> +	writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
> +	writel(0x00000001, MVEBU_MPP_BASE + 0x10);
> +
> +	/* Set GPP Out value */
> +	writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
> +	writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
> +
> +	/* Set GPP Polarity */
> +	writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
> +	writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
> +
> +	/* Set GPP Out Enable */
> +	writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
> +	writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
> +
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	/* address of boot parameters */
> +	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> +
> +	/* Disable MBUS Err Prop - in order to avoid data aborts */
> +	clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8));

Is this some change that should be done for all "MSYS" boards?
If yes, then please move it to arch/arm/mach-mvebu instead.

> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_DISPLAY_BOARDINFO
> +int checkboard(void)
> +{
> +	puts("Board: " CONFIG_SYS_BOARD "\n");
> +
> +	return 0;
> +}
> +#endif
> diff --git a/board/Marvell/db-xc3-24g4xg/kwbimage.cfg b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> new file mode 100644
> index 000000000000..b8bb7a6eb75b
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> @@ -0,0 +1,12 @@
> +#
> +# Copyright (C) 2014 Stefan Roese <sr@denx.de>
> +#
> +
> +# Armada XP uses version 1 image format
> +VERSION		1
> +
> +# Boot Media configurations
> +BOOT_FROM	spi
> +
> +# Binary Header (bin_hdr) with DDR3 training code
> +BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068
> diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig
> new file mode 100644
> index 000000000000..0285ccaa365c
> --- /dev/null
> +++ b/configs/db-xc3-24g4xg_defconfig
> @@ -0,0 +1,55 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MVEBU=y
> +CONFIG_SYS_TEXT_BASE=0x00800000
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_TARGET_DB_XC3_24G4XG=y
> +CONFIG_BUILD_TARGET="u-boot.kwb"
> +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_SYS_ALT_MEMTEST=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_TFTPPUT=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_CMD_UBI=y
> +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg"
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_SPL_OF_TRANSLATE=y
> +CONFIG_BLK=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MVTWSI=y
> +# CONFIG_MMC is not set
> +CONFIG_MTD=y
> +CONFIG_MTD_DEVICE=y
> +CONFIG_NAND=y
> +CONFIG_NAND_PXA3XX=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_SST=y
> +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
> +CONFIG_PCI=y
> +CONFIG_PCI_MVEBU=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_KIRKWOOD_SPI=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_HOST_ETHER=y
> +CONFIG_USB_ETHER_ASIX=y
> +CONFIG_USB_ETHER_RTL8152=y
> +CONFIG_USB_ETHER_SMSC95XX=y
> diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h
> new file mode 100644
> index 000000000000..2638ff9d7577
> --- /dev/null
> +++ b/include/configs/db-xc3-24g4xg.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2014 Stefan Roese <sr@denx.de>
> + */
> +
> +#ifndef _CONFIG_DB_XC3_24G4G_H
> +#define _CONFIG_DB_XC3_24G4G_H
> +
> +/*
> + * High Level Configuration Options (easy to change)
> + */
> +
> +#define CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
> +#define CONFIG_SYS_TCLK		200000000	/* 200MHz */
> +
> +/* SPI NOR flash default params, used by sf commands */
> +#define CONFIG_SF_DEFAULT_SPEED		1000000
> +#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3

Do we still need these with the recent SPI flash changes? I
did not test, I'm just curious, if those can be omitted and
everything necessary gets extraced from the DT instead?

> +
> +/* USB/EHCI configuration */
> +#define CONFIG_EHCI_IS_TDI
> +
> +/* Environment in SPI NOR flash */
> +#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
> +#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
> +#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
> +
> +/* NAND */
> +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +
> +/* Keep device tree and initrd in lower memory so the kernel can access them */
> +#define CONFIG_EXTRA_ENV_SETTINGS	\
> +	"fdt_high=0x10000000\0"		\
> +	"initrd_high=0x10000000\0"
> +
> +/*
> + * mv-common.h should be defined after CMD configs since it used them
> + * to enable certain macros
> + */
> +#include "mv-common.h"
> +#undef CONFIG_SYS_MAXARGS
> +#define CONFIG_SYS_MAXARGS 96
> +
> +#endif /* _CONFIG_DB_XC3_24G4G_H */
> diff --git a/tools/Makefile b/tools/Makefile
> index 081383d7a790..463f165f9572 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -148,6 +148,10 @@ ifneq ($(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),)
>   HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE
>   endif
>   
> +ifneq ($(CONFIG_MSYS),)
> +HOSTCFLAGS_kwbimage.o += -DCONFIG_MSYS
> +endif
> +

Again, please move into a seperate patch.

>   # MXSImage needs LibSSL
>   ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE),)
>   HOSTLOADLIBES_mkimage += \
> diff --git a/tools/kwbimage.c b/tools/kwbimage.c
> index a88a3830c0c8..8d60dc001112 100644
> --- a/tools/kwbimage.c
> +++ b/tools/kwbimage.c
> @@ -1252,8 +1252,12 @@ static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
>   		cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
>   	main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
>   	main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
> +#ifdef CONFIG_MSYS
> +	main_hdr->destaddr     = cpu_to_le32(params->addr);
> +#else
>   	main_hdr->destaddr     = cpu_to_le32(params->addr)

Why is this change necessary? Could you please explain?

Thanks,
Stefan
Chris Packham Feb. 15, 2019, 12:18 p.m. UTC | #2 
On Fri, 15 Feb 2019, 11:17 PM Stefan Roese <sr@denx.de wrote:

> Hi Chris,
>
> please find a few comments / questions below.
>
> On 15.02.19 10:41, Chris Packham wrote:
> > From: Chris Packham <chris.packham@alliedtelesis.co.nz>
> >
> > The DB-XC3-24G4XG is a switch development board from Marvell. It can
> > either use and external CPU card such as the db-88f6820-amc or the
> > internal CPU that is integrated into the switch.
> >
> > Add support for running U-Boot on the internal CPU and enable the USB,
> > SPI and NAND peripherals. For now this needs the bin_hdr from the
> > Marvell U-Boot for this board.
> >
> > Signed-off-by: Chris Packham <judge.packham@gmail.com>
> > ---
> >
> >   arch/arm/dts/Makefile                       |   3 +-
> >   arch/arm/dts/armada-xp-98dx3236.dtsi        | 343 ++++++++++++++++++++
> >   arch/arm/dts/armada-xp-98dx3336.dtsi        |  39 +++
> >   arch/arm/dts/armada-xp-98dx4251.dtsi        |  54 +++
> >   arch/arm/dts/armada-xp-db-xc3-24g4xg.dts    | 122 +++++++
> >   arch/arm/mach-mvebu/Kconfig                 |   8 +
> >   board/Marvell/db-xc3-24g4xg/MAINTAINERS     |   7 +
> >   board/Marvell/db-xc3-24g4xg/Makefile        |   5 +
> >   board/Marvell/db-xc3-24g4xg/README          |   4 +
> >   board/Marvell/db-xc3-24g4xg/binary.0        |  11 +
> >   board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c |  71 ++++
> >   board/Marvell/db-xc3-24g4xg/kwbimage.cfg    |  12 +
> >   configs/db-xc3-24g4xg_defconfig             |  55 ++++
> >   include/configs/db-xc3-24g4xg.h             |  45 +++
> >   tools/Makefile                              |   4 +
> >   tools/kwbimage.c                            |   4 +
>
> Could you please split the kwbimage tool changes into a separate
> patch?
>

Yes will do.


> >   16 files changed, 786 insertions(+), 1 deletion(-)
> >   create mode 100644 arch/arm/dts/armada-xp-98dx3236.dtsi
> >   create mode 100644 arch/arm/dts/armada-xp-98dx3336.dtsi
> >   create mode 100644 arch/arm/dts/armada-xp-98dx4251.dtsi
> >   create mode 100644 arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> >   create mode 100644 board/Marvell/db-xc3-24g4xg/MAINTAINERS
> >   create mode 100644 board/Marvell/db-xc3-24g4xg/Makefile
> >   create mode 100644 board/Marvell/db-xc3-24g4xg/README
> >   create mode 100644 board/Marvell/db-xc3-24g4xg/binary.0
> >   create mode 100644 board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> >   create mode 100644 board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> >   create mode 100644 configs/db-xc3-24g4xg_defconfig
> >   create mode 100644 include/configs/db-xc3-24g4xg.h
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index ca5062348087..133f09d8ba63 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -113,7 +113,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=                       \
> >       armada-xp-theadorable.dtb               \
> >       armada-38x-controlcenterdc.dtb          \
> >       armada-385-atl-x530.dtb                 \
> > -     armada-385-atl-x530DP.dtb
> > +     armada-385-atl-x530DP.dtb               \
> > +     armada-xp-db-xc3-24g4xg.dtb
> >
> >   dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
> >       uniphier-ld11-global.dtb \
> > diff --git a/arch/arm/dts/armada-xp-98dx3236.dtsi
> b/arch/arm/dts/armada-xp-98dx3236.dtsi
> > new file mode 100644
> > index 000000000000..5df1d1848dbc
> > --- /dev/null
> > +++ b/arch/arm/dts/armada-xp-98dx3236.dtsi
> > @@ -0,0 +1,343 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree Include file for Marvell 98dx3236 family SoC
> > + *
> > + * Copyright (C) 2016 Allied Telesis Labs
> > + *
> > + * Contains definitions specific to the 98dx3236 SoC that are not
> > + * common to all Armada XP SoCs.
> > + */
> > +
> > +#include "armada-370-xp.dtsi"
> > +
> > +/ {
> > +     #address-cells = <2>;
> > +     #size-cells = <2>;
> > +
> > +     model = "Marvell 98DX3236 SoC";
> > +     compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> > +
> > +     aliases {
> > +             gpio0 = &gpio0;
> > +             gpio1 = &gpio1;
> > +             gpio2 = &gpio2;
> > +     };
> > +
> > +     cpus {
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +             enable-method = "marvell,98dx3236-smp";
> > +
> > +             cpu@0 {
> > +                     device_type = "cpu";
> > +                     compatible = "marvell,sheeva-v7";
> > +                     reg = <0>;
> > +                     clocks = <&cpuclk 0>;
> > +                     clock-latency = <1000000>;
> > +             };
> > +     };
> > +
> > +     soc {
> > +             compatible = "marvell,armadaxp-mbus", "simple-bus";
> > +
> > +             ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> > +                       MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> > +                       MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> > +                       MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> > +                       MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> > +
> > +             bootrom {
> > +                     compatible = "marvell,bootrom";
> > +                     reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
> > +             };
> > +
> > +             /*
> > +              * 98DX3236 has 1 x1 PCIe unit Gen2.0
> > +              */
> > +             pciec: pcie@82000000 {
> > +                     compatible = "marvell,armada-xp-pcie";
> > +                     status = "disabled";
> > +                     device_type = "pci";
> > +
> > +                     #address-cells = <3>;
> > +                     #size-cells = <2>;
> > +
> > +                     msi-parent = <&mpic>;
> > +                     bus-range = <0x00 0xff>;
> > +
> > +                     ranges =
> > +                            <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01)
> 0x40000 0 0x00002000   /* Port 0.0 registers */
> > +                             0x82000000 0x1 0       MBUS_ID(0x04, 0xe8)
> 0 1 0 /* Port 0.0 MEM */
> > +                             0x81000000 0x1 0       MBUS_ID(0x04, 0xe0)
> 0 1 0 /* Port 0.0 IO  */>;
> > +
> > +                     pcie1: pcie@1,0 {
> > +                             device_type = "pci";
> > +                             assigned-addresses = <0x82000800 0 0x40000
> 0 0x2000>;
> > +                             reg = <0x0800 0 0 0 0>;
> > +                             #address-cells = <3>;
> > +                             #size-cells = <2>;
> > +                             #interrupt-cells = <1>;
> > +                             ranges = <0x82000000 0 0 0x82000000 0x1 0
> 1 0
> > +                                       0x81000000 0 0 0x81000000 0x1 0
> 1 0>;
> > +                             bus-range = <0x00 0xff>;
> > +                             interrupt-map-mask = <0 0 0 0>;
> > +                             interrupt-map = <0 0 0 0 &mpic 58>;
> > +                             marvell,pcie-port = <0>;
> > +                             marvell,pcie-lane = <0>;
> > +                             clocks = <&gateclk 5>;
> > +                             status = "disabled";
> > +                     };
> > +             };
> > +
> > +             internal-regs {
> > +                     sdramc: sdramc@1400 {
> > +                             compatible =
> "marvell,armada-xp-sdram-controller";
> > +                             reg = <0x1400 0x500>;
> > +                     };
> > +
> > +                     L2: l2-cache@8000 {
> > +                             compatible = "marvell,aurora-system-cache";
> > +                             reg = <0x08000 0x1000>;
> > +                             cache-id-part = <0x100>;
> > +                             cache-level = <2>;
> > +                             cache-unified;
> > +                             wt-override;
> > +                     };
> > +
> > +                     gpio0: gpio@18100 {
> > +                             compatible = "marvell,orion-gpio";
> > +                             reg = <0x18100 0x40>;
> > +                             ngpios = <32>;
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                             interrupts = <82>, <83>, <84>, <85>;
> > +                     };
> > +
> > +                     /* does not exist */
> > +                     gpio1: gpio@18140 {
> > +                             compatible = "marvell,orion-gpio";
> > +                             reg = <0x18140 0x40>;
> > +                             status = "disabled";
> > +                     };
> > +
> > +                     gpio2: gpio@18180 { /* rework some properties */
> > +                             compatible = "marvell,orion-gpio";
> > +                             reg = <0x18180 0x40>;
> > +                             ngpios = <1>; /* only gpio #32 */
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                             interrupts = <87>;
> > +                     };
> > +
> > +                     systemc: system-controller@18200 {
> > +                             compatible =
> "marvell,armada-370-xp-system-controller";
> > +                             reg = <0x18200 0x500>;
> > +                     };
> > +
> > +                     gateclk: clock-gating-control@18220 {
> > +                             compatible =
> "marvell,mv98dx3236-gating-clock";
> > +                             reg = <0x18220 0x4>;
> > +                             clocks = <&coreclk 0>;
> > +                             #clock-cells = <1>;
> > +                     };
> > +
> > +                     cpuclk: clock-complex@18700 {
> > +                             #clock-cells = <1>;
> > +                             compatible =
> "marvell,mv98dx3236-cpu-clock";
> > +                             reg = <0x18700 0x24>, <0x1c054 0x10>;
> > +                             clocks = <&coreclk 1>;
> > +                     };
> > +
> > +                     corediv-clock@18740 {
> > +                             status = "disabled";
> > +                     };
> > +
> > +                     cpu-config@21000 {
> > +                             compatible =
> "marvell,armada-xp-cpu-config";
> > +                             reg = <0x21000 0x8>;
> > +                     };
> > +
> > +                     ethernet@70000 {
> > +                             compatible = "marvell,armada-xp-neta";
> > +                     };
> > +
> > +                     ethernet@74000 {
> > +                             compatible = "marvell,armada-xp-neta";
> > +                     };
> > +
> > +                     xor1: xor@f0800 {
> > +                             compatible = "marvell,orion-xor";
> > +                             reg = <0xf0800 0x100
> > +                                    0xf0a00 0x100>;
> > +                             clocks = <&gateclk 22>;
> > +                             status = "okay";
> > +
> > +                             xor10 {
> > +                                     interrupts = <51>;
> > +                                     dmacap,memcpy;
> > +                                     dmacap,xor;
> > +                             };
> > +                             xor11 {
> > +                                     interrupts = <52>;
> > +                                     dmacap,memcpy;
> > +                                     dmacap,xor;
> > +                                     dmacap,memset;
> > +                             };
> > +                     };
> > +
> > +                     nand_controller: nand@d0000 {
> > +                             clocks = <&dfx_coredivclk 0>;
> > +                     };
> > +
> > +                     xor0: xor@f0900 {
> > +                             compatible = "marvell,orion-xor";
> > +                             reg = <0xF0900 0x100
> > +                                    0xF0B00 0x100>;
> > +                             clocks = <&gateclk 28>;
> > +                             status = "okay";
> > +
> > +                             xor00 {
> > +                                     interrupts = <94>;
> > +                                     dmacap,memcpy;
> > +                                     dmacap,xor;
> > +                             };
> > +                             xor01 {
> > +                                     interrupts = <95>;
> > +                                     dmacap,memcpy;
> > +                                     dmacap,xor;
> > +                                     dmacap,memset;
> > +                             };
> > +                     };
> > +             };
> > +
> > +             dfx: dfx-server@ac000000 {
> > +                     compatible = "marvell,dfx-server", "simple-bus";
> > +                     #address-cells = <1>;
> > +                     #size-cells = <1>;
> > +                     ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
> > +                     reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
> > +
> > +                        thermal: thermal@f8078 {
> > +                                compatible =
> "marvell,armada380-thermal";
> > +                                reg = <0xf8078 0x4>, <0xf8074 0x4>;
> > +                                status = "okay";
> > +                        };
> > +
> > +                     coreclk: mvebu-sar@f8204 {
> > +                             compatible =
> "marvell,mv98dx3236-core-clock";
> > +                             reg = <0xf8204 0x4>;
> > +                             #clock-cells = <1>;
> > +                     };
> > +
> > +                     dfx_coredivclk: corediv-clock@f8268 {
> > +                             compatible =
> "marvell,mv98dx3236-corediv-clock";
> > +                             reg = <0xf8268 0xc>;
> > +                             #clock-cells = <1>;
> > +                             clocks = <&mainpll>;
> > +                             clock-output-names = "nand";
> > +                     };
> > +             };
> > +
> > +             switch: switch@a8000000 {
> > +                     compatible = "simple-bus";
> > +                     #address-cells = <1>;
> > +                     #size-cells = <1>;
> > +                     ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
> > +
> > +                     pp0: packet-processor@0 {
> > +                             compatible = "marvell,prestera-98dx3236",
> "marvell,prestera";
> > +                             reg = <0 0x4000000>;
> > +                             interrupts = <33>, <34>, <35>;
> > +                             dfx = <&dfx>;
> > +                     };
> > +             };
> > +     };
> > +
> > +     clocks {
> > +             /* 25 MHz reference crystal */
> > +             refclk: oscillator {
> > +                     compatible = "fixed-clock";
> > +                     #clock-cells = <0>;
> > +                     clock-frequency = <25000000>;
> > +             };
> > +     };
> > +};
> > +
> > +&i2c0 {
> > +     compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
> > +     reg = <0x11000 0x100>;
> > +};
> > +
> > +&i2c1 {
> > +     compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
> > +     reg = <0x11100 0x100>;
> > +};
> > +
> > +&mpic {
> > +     reg = <0x20a00 0x2d0>, <0x21070 0x58>;
> > +};
> > +
> > +&rtc {
> > +     status = "disabled";
> > +};
> > +
> > +&timer {
> > +     compatible = "marvell,armada-xp-timer";
> > +     clocks = <&coreclk 2>, <&refclk>;
> > +     clock-names = "nbclk", "fixed";
> > +};
> > +
> > +&watchdog {
> > +     compatible = "marvell,armada-xp-wdt";
> > +     clocks = <&coreclk 2>, <&refclk>;
> > +     clock-names = "nbclk", "fixed";
> > +};
> > +
> > +&cpurst {
> > +     reg = <0x20800 0x20>;
> > +};
> > +
> > +&usb0 {
> > +     clocks = <&gateclk 18>;
> > +};
> > +
> > +&usb1 {
> > +     clocks = <&gateclk 19>;
> > +};
> > +
> > +&pinctrl {
> > +     compatible = "marvell,98dx3236-pinctrl";
> > +
> > +     nand_pins: nand-pins {
> > +             marvell,pins = "mpp20", "mpp21", "mpp22",
> > +                            "mpp23", "mpp24", "mpp25",
> > +                            "mpp26", "mpp27", "mpp28",
> > +                            "mpp29", "mpp30";
> > +             marvell,function = "dev";
> > +     };
> > +
> > +     nand_rb: nand-rb {
> > +             marvell,pins = "mpp19";
> > +             marvell,function = "nand";
> > +     };
> > +
> > +     spi0_pins: spi0-pins {
> > +             marvell,pins = "mpp0", "mpp1",
> > +                            "mpp2", "mpp3";
> > +             marvell,function = "spi0";
> > +     };
> > +};
> > +
> > +&spi0 {
> > +     compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
> > +     pinctrl-0 = <&spi0_pins>;
> > +     pinctrl-names = "default";
> > +};
> > +
> > +&sdio {
> > +     status = "disabled";
> > +};
> > diff --git a/arch/arm/dts/armada-xp-98dx3336.dtsi
> b/arch/arm/dts/armada-xp-98dx3336.dtsi
> > new file mode 100644
> > index 000000000000..1d9d8a8ea60c
> > --- /dev/null
> > +++ b/arch/arm/dts/armada-xp-98dx3336.dtsi
> > @@ -0,0 +1,39 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree Include file for Marvell 98dx3336 family SoC
> > + *
> > + * Copyright (C) 2016 Allied Telesis Labs
> > + *
> > + * Contains definitions specific to the 98dx3236 SoC that are not
> > + * common to all Armada XP SoCs.
> > + */
> > +
> > +#include "armada-xp-98dx3236.dtsi"
> > +
> > +/ {
> > +     model = "Marvell 98DX3336 SoC";
> > +     compatible = "marvell,armadaxp-98dx3336",
> "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> > +
> > +     cpus {
> > +             cpu@1 {
> > +                     device_type = "cpu";
> > +                     compatible = "marvell,sheeva-v7";
> > +                     reg = <1>;
> > +                     clocks = <&cpuclk 1>;
> > +                     clock-latency = <1000000>;
> > +             };
> > +     };
> > +
> > +     soc {
> > +             internal-regs {
> > +                     resume@20980 {
> > +                             compatible =
> "marvell,98dx3336-resume-ctrl";
> > +                             reg = <0x20980 0x10>;
> > +                     };
> > +             };
> > +     };
> > +};
> > +
> > +&pp0 {
> > +     compatible = "marvell,prestera-98dx3336", "marvell,prestera";
> > +};
> > diff --git a/arch/arm/dts/armada-xp-98dx4251.dtsi
> b/arch/arm/dts/armada-xp-98dx4251.dtsi
> > new file mode 100644
> > index 000000000000..48ffdc72bfc7
> > --- /dev/null
> > +++ b/arch/arm/dts/armada-xp-98dx4251.dtsi
> > @@ -0,0 +1,54 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree Include file for Marvell 98dx4521 family SoC
> > + *
> > + * Copyright (C) 2016 Allied Telesis Labs
> > + *
> > + * Contains definitions specific to the 98dx4521 SoC that are not
> > + * common to all Armada XP SoCs.
> > + */
> > +
> > +#include "armada-xp-98dx3236.dtsi"
> > +
> > +/ {
> > +     model = "Marvell 98DX4251 SoC";
> > +     compatible = "marvell,armadaxp-98dx4251",
> "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> > +
> > +     cpus {
> > +             cpu@1 {
> > +                     device_type = "cpu";
> > +                     compatible = "marvell,sheeva-v7";
> > +                     reg = <1>;
> > +                     clocks = <&cpuclk 1>;
> > +                     clock-latency = <1000000>;
> > +             };
> > +     };
> > +
> > +     soc {
> > +             internal-regs {
> > +                     resume@20980 {
> > +                             compatible =
> "marvell,98dx3336-resume-ctrl";
> > +                             reg = <0x20980 0x10>;
> > +                     };
> > +             };
> > +     };
> > +};
> > +
> > +&sdio {
> > +     status = "okay";
> > +};
> > +
> > +&pinctrl {
> > +     compatible = "marvell,98dx4251-pinctrl";
> > +
> > +     sdio_pins: sdio-pins {
> > +             marvell,pins = "mpp5", "mpp6", "mpp7",
> > +                            "mpp8", "mpp9", "mpp10";
> > +             marvell,function = "sd0";
> > +     };
> > +};
> > +
> > +&pp0 {
> > +     compatible = "marvell,prestera-98dx4251", "marvell,prestera";
> > +     interrupts = <33>, <34>, <35>, <36>;
> > +};
> > diff --git a/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> > new file mode 100644
> > index 000000000000..2daf83e655ac
> > --- /dev/null
> > +++ b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> > @@ -0,0 +1,122 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree file for DB-XC3-24G4XG board
> > + *
> > + * Copyright (C) 2016 Allied Telesis Labs
> > + *
> > + * Based on armada-xp-db.dts
> > + *
> > + * Note: this Device Tree assumes that the bootloader has remapped the
> > + * internal registers to 0xf1000000 (instead of the default
> > + * 0xd0000000). The 0xf1000000 is the default used by the recent,
> > + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
> > + * boards were delivered with an older version of the bootloader that
> > + * left internal registers mapped at 0xd0000000. If you are in this
> > + * situation, you should either update your bootloader (preferred
> > + * solution) or the below Device Tree should be adjusted.
> > + */
> > +
> > +/dts-v1/;
> > +#include "armada-xp-98dx3336.dtsi"
> > +
> > +/ {
> > +     model = "DB-XC3-24G4XG";
> > +     compatible = "marvell,armadaxp-98dx3336",
> "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +             bootargs = "console=ttyS0,115200 earlyprintk";
> > +     };
> > +
> > +     aliases {
> > +             spi0 = &spi0;
> > +     };
> > +
> > +     memory {
> > +             device_type = "memory";
> > +             reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
> > +     };
> > +};
> > +
> > +&L2 {
> > +     arm,parity-enable;
> > +     marvell,ecc-enable;
> > +};
> > +
> > +&devbus_bootcs {
> > +     status = "okay";
> > +
> > +     /* Device Bus parameters are required */
> > +
> > +     /* Read parameters */
> > +     devbus,bus-width    = <16>;
> > +     devbus,turn-off-ps  = <60000>;
> > +     devbus,badr-skew-ps = <0>;
> > +     devbus,acc-first-ps = <124000>;
> > +     devbus,acc-next-ps  = <248000>;
> > +     devbus,rd-setup-ps  = <0>;
> > +     devbus,rd-hold-ps   = <0>;
> > +
> > +     /* Write parameters */
> > +     devbus,sync-enable = <0>;
> > +     devbus,wr-high-ps  = <60000>;
> > +     devbus,wr-low-ps   = <60000>;
> > +     devbus,ale-wr-ps   = <60000>;
> > +};
> > +
> > +&uart0 {
> > +     status = "okay";
> > +     u-boot,dm-pre-reloc;
>
> All U-Boot specific DT properties into a *-u-boot.dtsi file please.
>
> > +};
> > +
> > +&uart1 {
> > +     status = "okay";
> > +};
> > +
> > +&i2c0 {
> > +     clock-frequency = <100000>;
> > +     status = "okay";
> > +};
> > +
> > +&nand_controller {
> > +     compatible="marvell,mvebu-pxa3xx-nand";
> > +     status = "okay";
> > +     label = "pxa3xx_nand-0";
> > +     nand-rb = <0>;
> > +     marvell,nand-keep-config;
> > +     nand-on-flash-bbt;
> > +     nand-ecc-strength = <4>;
> > +     nand-ecc-step-size = <512>;
> > +};
> > +
> > +&usb0 {
> > +     status = "okay";
> > +};
> > +
> > +&spi0 {
> > +     status = "okay";
> > +     u-boot,dm-pre-reloc;
>
> Here as well and all other occurrences too please.


> > +
> > +     spi-flash@0 {
> > +             #address-cells = <1>;
> > +             #size-cells = <1>;
> > +             compatible = "spi-flash", "jedec,spi-nor";
> > +             reg = <0>; /* Chip select 0 */
> > +             spi-max-frequency = <108000000>;
> > +             m25p,fast-read;
> > +
> > +             partition@u-boot {
> > +                     reg = <0x00000000 0x00100000>;
> > +                     label = "u-boot";
> > +             };
> > +             partition@u-boot-env {
> > +                     reg = <0x00100000 0x00040000>;
> > +                     label = "u-boot-env";
> > +             };
> > +             partition@unused {
> > +                     reg = <0x00140000 0x00ec0000>;
> > +                     label = "unused";
> > +             };
> > +
> > +     };
> > +};
> > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> > index 05aa2ade0499..938466615c66 100644
> > --- a/arch/arm/mach-mvebu/Kconfig
> > +++ b/arch/arm/mach-mvebu/Kconfig
> > @@ -152,6 +152,10 @@ config TARGET_X530
> >       bool "Support Allied Telesis x530"
> >       select 88F6820
> >
> > +config TARGET_DB_XC3_24G4XG
> > +     bool "Support DB-XC3-24G4XG"
> > +     select 98DX3336
> > +
> >   endchoice
> >
> >   config SYS_BOARD
> > @@ -170,6 +174,7 @@ config SYS_BOARD
> >       default "theadorable" if TARGET_THEADORABLE
> >       default "a38x" if TARGET_CONTROLCENTERDC
> >       default "x530" if TARGET_X530
> > +     default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> >
> >   config SYS_CONFIG_NAME
> >       default "clearfog" if TARGET_CLEARFOG
> > @@ -187,6 +192,7 @@ config SYS_CONFIG_NAME
> >       default "turris_mox" if TARGET_TURRIS_MOX
> >       default "controlcenterdc" if TARGET_CONTROLCENTERDC
> >       default "x530" if TARGET_X530
> > +     default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> >
> >   config SYS_VENDOR
> >       default "Marvell" if TARGET_DB_MV784MP_GP
> > @@ -195,6 +201,8 @@ config SYS_VENDOR
> >       default "Marvell" if TARGET_DB_88F6820_GP
> >       default "Marvell" if TARGET_DB_88F6820_AMC
> >       default "Marvell" if TARGET_MVEBU_ARMADA_8K
> > +     default "Marvell" if TARGET_DB_XC3_24G4XG
> > +     default "Marvell" if TARGET_MVEBU_DB_88F7040
> >       default "solidrun" if TARGET_CLEARFOG
> >       default "kobol" if TARGET_HELIOS4
> >       default "Synology" if TARGET_DS414
> > diff --git a/board/Marvell/db-xc3-24g4xg/MAINTAINERS
> b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
> > new file mode 100644
> > index 000000000000..94d4a901783b
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
> > @@ -0,0 +1,7 @@
> > +DB-XC3-24G4XG BOARD
> > +M:   Chris Packham <chris.packham@alliedtelesis.co.nz>
> > +S:   Maintained
> > +F:   board/Marvell/db-xc3-24g4xg/
> > +F:   include/configs/db-xc3-24g4xg.h
> > +F:   configs/db-xc3-24g4xg-amc_defconfig
> > +F:   arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> > diff --git a/board/Marvell/db-xc3-24g4xg/Makefile
> b/board/Marvell/db-xc3-24g4xg/Makefile
> > new file mode 100644
> > index 000000000000..199837a84fe6
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/Makefile
> > @@ -0,0 +1,5 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright (C) 2015 Stefan Roese <sr@denx.de>
> > +
> > +obj-y        := db-xc3-24g4xg.o
> > diff --git a/board/Marvell/db-xc3-24g4xg/README
> b/board/Marvell/db-xc3-24g4xg/README
> > new file mode 100644
> > index 000000000000..5e479b433e4d
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/README
> > @@ -0,0 +1,4 @@
> > +To generate binary.0 from Marvell's bin_hdr.elf use the following
> command
> > +
> > +    arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \
> > +       board/Marvell/db-xc3-24g4xg/binary.0
> > diff --git a/board/Marvell/db-xc3-24g4xg/binary.0
> b/board/Marvell/db-xc3-24g4xg/binary.0
> > new file mode 100644
> > index 000000000000..8dd687286a00
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/binary.0
> > @@ -0,0 +1,11 @@
> > +--------
> > +WARNING:
> > +--------
> > +This file should contain the bin_hdr generated by the original Marvell
> > +U-Boot implementation. As this is currently not included in this
> > +U-Boot version, we have added this placeholder, so that the U-Boot
> > +image can be generated without errors.
> > +
> > +If you have a known to be working bin_hdr for your board, then you
> > +just need to replace this text file here with the binary header
> > +and recompile U-Boot.
> > diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> > new file mode 100644
> > index 000000000000..428e3f611798
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> > @@ -0,0 +1,71 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2015 Stefan Roese <sr@denx.de>
> > + */
> > +
> > +#include <common.h>
> > +#include <i2c.h>
> > +#include <asm/gpio.h>
> > +#include <linux/mbus.h>
> > +#include <linux/io.h>
> > +#include <asm/arch/cpu.h>
> > +#include <asm/arch/soc.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +/*
> > + * These values and defines are taken from the Marvell U-Boot version
> > + * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
> > + */
> > +#define DB_DX_AC3_GPP_OUT_ENA_LOW    (~(BIT(0) | BIT(2) | BIT(3) |
> BIT(4) | BIT(6) | BIT(12) \
> > +                                     | BIT(13) | BIT(16) | BIT(17) |
> BIT(20) | BIT(29)  | BIT(30)))
> > +#define DB_DX_AC3_GPP_OUT_ENA_MID    (~(0))
> > +#define DB_DX_AC3_GPP_OUT_VAL_LOW    (BIT(0) | BIT(2) | BIT(3) | BIT(4)
> | BIT(6) | BIT(12) \
> > +                                     | BIT(13) | BIT(16) | BIT(17) |
> BIT(20) | BIT(29)  | BIT(30))
> > +#define DB_DX_AC3_GPP_OUT_VAL_MID    0x0
> > +#define DB_DX_AC3_GPP_POL_LOW                0x0
> > +#define DB_DX_AC3_GPP_POL_MID                0x0
> > +
> > +int board_early_init_f(void)
> > +{
> > +     /* Configure MPP */
> > +     writel(0x00142222, MVEBU_MPP_BASE + 0x00);
> > +     writel(0x11122000, MVEBU_MPP_BASE + 0x04);
> > +     writel(0x44444004, MVEBU_MPP_BASE + 0x08);
> > +     writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
> > +     writel(0x00000001, MVEBU_MPP_BASE + 0x10);
> > +
> > +     /* Set GPP Out value */
> > +     writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
> > +     writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
> > +
> > +     /* Set GPP Polarity */
> > +     writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
> > +     writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
> > +
> > +     /* Set GPP Out Enable */
> > +     writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
> > +     writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
> > +
> > +     return 0;
> > +}
> > +
> > +int board_init(void)
> > +{
> > +     /* address of boot parameters */
> > +     gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> > +
> > +     /* Disable MBUS Err Prop - in order to avoid data aborts */
> > +     clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8));
>
> Is this some change that should be done for all "MSYS" boards?
> If yes, then please move it to arch/arm/mach-mvebu instead.
>

Yes. I'll find a better home for it.


> > +
> > +     return 0;
> > +}
> > +
> > +#ifdef CONFIG_DISPLAY_BOARDINFO
> > +int checkboard(void)
> > +{
> > +     puts("Board: " CONFIG_SYS_BOARD "\n");
> > +
> > +     return 0;
> > +}
> > +#endif
> > diff --git a/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> > new file mode 100644
> > index 000000000000..b8bb7a6eb75b
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> > @@ -0,0 +1,12 @@
> > +#
> > +# Copyright (C) 2014 Stefan Roese <sr@denx.de>
> > +#
> > +
> > +# Armada XP uses version 1 image format
> > +VERSION              1
> > +
> > +# Boot Media configurations
> > +BOOT_FROM    spi
> > +
> > +# Binary Header (bin_hdr) with DDR3 training code
> > +BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068
> > diff --git a/configs/db-xc3-24g4xg_defconfig
> b/configs/db-xc3-24g4xg_defconfig
> > new file mode 100644
> > index 000000000000..0285ccaa365c
> > --- /dev/null
> > +++ b/configs/db-xc3-24g4xg_defconfig
> > @@ -0,0 +1,55 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_MVEBU=y
> > +CONFIG_SYS_TEXT_BASE=0x00800000
> > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_TARGET_DB_XC3_24G4XG=y
> > +CONFIG_BUILD_TARGET="u-boot.kwb"
> > +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> > +CONFIG_CMD_MEMTEST=y
> > +CONFIG_SYS_ALT_MEMTEST=y
> > +# CONFIG_CMD_FLASH is not set
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_SF=y
> > +CONFIG_CMD_SPI=y
> > +CONFIG_CMD_USB=y
> > +# CONFIG_CMD_SETEXPR is not set
> > +CONFIG_CMD_DHCP=y
> > +CONFIG_CMD_TFTPPUT=y
> > +CONFIG_CMD_MII=y
> > +CONFIG_CMD_PING=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_TIME=y
> > +CONFIG_CMD_EXT2=y
> > +CONFIG_CMD_EXT4=y
> > +CONFIG_CMD_FAT=y
> > +CONFIG_CMD_FS_GENERIC=y
> > +CONFIG_CMD_UBI=y
> > +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg"
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_SPL_OF_TRANSLATE=y
> > +CONFIG_BLK=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_MVTWSI=y
> > +# CONFIG_MMC is not set
> > +CONFIG_MTD=y
> > +CONFIG_MTD_DEVICE=y
> > +CONFIG_NAND=y
> > +CONFIG_NAND_PXA3XX=y
> > +CONFIG_SPI_FLASH=y
> > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_SPI_FLASH_STMICRO=y
> > +CONFIG_SPI_FLASH_SST=y
> > +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
> > +CONFIG_PCI=y
> > +CONFIG_PCI_MVEBU=y
> > +CONFIG_SYS_NS16550=y
> > +CONFIG_KIRKWOOD_SPI=y
> > +CONFIG_USB=y
> > +CONFIG_DM_USB=y
> > +CONFIG_USB_EHCI_HCD=y
> > +CONFIG_USB_STORAGE=y
> > +CONFIG_USB_HOST_ETHER=y
> > +CONFIG_USB_ETHER_ASIX=y
> > +CONFIG_USB_ETHER_RTL8152=y
> > +CONFIG_USB_ETHER_SMSC95XX=y
> > diff --git a/include/configs/db-xc3-24g4xg.h
> b/include/configs/db-xc3-24g4xg.h
> > new file mode 100644
> > index 000000000000..2638ff9d7577
> > --- /dev/null
> > +++ b/include/configs/db-xc3-24g4xg.h
> > @@ -0,0 +1,45 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2014 Stefan Roese <sr@denx.de>
> > + */
> > +
> > +#ifndef _CONFIG_DB_XC3_24G4G_H
> > +#define _CONFIG_DB_XC3_24G4G_H
> > +
> > +/*
> > + * High Level Configuration Options (easy to change)
> > + */
> > +
> > +#define CONFIG_SYS_KWD_CONFIG        $(CONFIG_BOARDDIR)/kwbimage.cfg
> > +#define CONFIG_SYS_TCLK              200000000       /* 200MHz */
> > +
> > +/* SPI NOR flash default params, used by sf commands */
> > +#define CONFIG_SF_DEFAULT_SPEED              1000000
> > +#define CONFIG_SF_DEFAULT_MODE               SPI_MODE_3
>
> Do we still need these with the recent SPI flash changes? I
> did not test, I'm just curious, if those can be omitted and
> everything necessary gets extraced from the DT instead?
>

I wasn't sure so i left it in. You're probably right so I'll drop it if i
can.


> > +
> > +/* USB/EHCI configuration */
> > +#define CONFIG_EHCI_IS_TDI
> > +
> > +/* Environment in SPI NOR flash */
> > +#define CONFIG_ENV_OFFSET            (1 << 20) /* 1MiB in */
> > +#define CONFIG_ENV_SIZE                      (64 << 10) /* 64KiB */
> > +#define CONFIG_ENV_SECT_SIZE         (256 << 10) /* 256KiB sectors */
> > +
> > +/* NAND */
> > +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> > +#define CONFIG_SYS_NAND_ONFI_DETECTION
> > +
> > +/* Keep device tree and initrd in lower memory so the kernel can access
> them */
> > +#define CONFIG_EXTRA_ENV_SETTINGS    \
> > +     "fdt_high=0x10000000\0"         \
> > +     "initrd_high=0x10000000\0"
> > +
> > +/*
> > + * mv-common.h should be defined after CMD configs since it used them
> > + * to enable certain macros
> > + */
> > +#include "mv-common.h"
> > +#undef CONFIG_SYS_MAXARGS
> > +#define CONFIG_SYS_MAXARGS 96
> > +
> > +#endif /* _CONFIG_DB_XC3_24G4G_H */
> > diff --git a/tools/Makefile b/tools/Makefile
> > index 081383d7a790..463f165f9572 100644
> > --- a/tools/Makefile
> > +++ b/tools/Makefile
> > @@ -148,6 +148,10 @@ ifneq ($(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),)
> >   HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE
> >   endif
> >
> > +ifneq ($(CONFIG_MSYS),)
> > +HOSTCFLAGS_kwbimage.o += -DCONFIG_MSYS
> > +endif
> > +
>
> Again, please move into a seperate patch.
>
> >   # MXSImage needs LibSSL
> >   ifneq
> ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE),)
> >   HOSTLOADLIBES_mkimage += \
> > diff --git a/tools/kwbimage.c b/tools/kwbimage.c
> > index a88a3830c0c8..8d60dc001112 100644
> > --- a/tools/kwbimage.c
> > +++ b/tools/kwbimage.c
> > @@ -1252,8 +1252,12 @@ static void *image_create_v1(size_t *imagesz,
> struct image_tool_params *params,
> >               cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
> >       main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
> >       main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
> > +#ifdef CONFIG_MSYS
> > +     main_hdr->destaddr     = cpu_to_le32(params->addr);
> > +#else
> >       main_hdr->destaddr     = cpu_to_le32(params->addr)
>
> Why is this change necessary? Could you please explain?
>

Because of using binary.0 instead of an SPL. The code that introduced this
was dealing with an extra image header that is included before kwb is
generated so destaddr needs to account for that. Because I don't have a SPL
(yet) I'm just taking bin_hdr from the Marvell  u-boot and objcopying it to
get binary.0 which doesn't have the header so destaddr == execaddr.

I'll try and include this information int the commit message for the
kwbimage patch.


> Thanks,
> Stefan
>
diff mbox series

Patch

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ca5062348087..133f09d8ba63 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -113,7 +113,8 @@  dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-xp-theadorable.dtb		\
 	armada-38x-controlcenterdc.dtb		\
 	armada-385-atl-x530.dtb			\
-	armada-385-atl-x530DP.dtb
+	armada-385-atl-x530DP.dtb		\
+	armada-xp-db-xc3-24g4xg.dtb
 
 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
 	uniphier-ld11-global.dtb \
diff --git a/arch/arm/dts/armada-xp-98dx3236.dtsi b/arch/arm/dts/armada-xp-98dx3236.dtsi
new file mode 100644
index 000000000000..5df1d1848dbc
--- /dev/null
+++ b/arch/arm/dts/armada-xp-98dx3236.dtsi
@@ -0,0 +1,343 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Marvell 98dx3236 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-370-xp.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	model = "Marvell 98DX3236 SoC";
+	compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "marvell,98dx3236-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "marvell,sheeva-v7";
+			reg = <0>;
+			clocks = <&cpuclk 0>;
+			clock-latency = <1000000>;
+		};
+	};
+
+	soc {
+		compatible = "marvell,armadaxp-mbus", "simple-bus";
+
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
+			  MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
+			  MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
+
+		bootrom {
+			compatible = "marvell,bootrom";
+			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+		};
+
+		/*
+		 * 98DX3236 has 1 x1 PCIe unit Gen2.0
+		 */
+		pciec: pcie@82000000 {
+			compatible = "marvell,armada-xp-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			msi-parent = <&mpic>;
+			bus-range = <0x00 0xff>;
+
+			ranges =
+			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */>;
+
+			pcie1: pcie@1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
+				bus-range = <0x00 0xff>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &mpic 58>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 5>;
+				status = "disabled";
+			};
+		};
+
+		internal-regs {
+			sdramc: sdramc@1400 {
+				compatible = "marvell,armada-xp-sdram-controller";
+				reg = <0x1400 0x500>;
+			};
+
+			L2: l2-cache@8000 {
+				compatible = "marvell,aurora-system-cache";
+				reg = <0x08000 0x1000>;
+				cache-id-part = <0x100>;
+				cache-level = <2>;
+				cache-unified;
+				wt-override;
+			};
+
+			gpio0: gpio@18100 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18100 0x40>;
+				ngpios = <32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <82>, <83>, <84>, <85>;
+			};
+
+			/* does not exist */
+			gpio1: gpio@18140 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18140 0x40>;
+				status = "disabled";
+			};
+
+			gpio2: gpio@18180 { /* rework some properties */
+				compatible = "marvell,orion-gpio";
+				reg = <0x18180 0x40>;
+				ngpios = <1>; /* only gpio #32 */
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <87>;
+			};
+
+			systemc: system-controller@18200 {
+				compatible = "marvell,armada-370-xp-system-controller";
+				reg = <0x18200 0x500>;
+			};
+
+			gateclk: clock-gating-control@18220 {
+				compatible = "marvell,mv98dx3236-gating-clock";
+				reg = <0x18220 0x4>;
+				clocks = <&coreclk 0>;
+				#clock-cells = <1>;
+			};
+
+			cpuclk: clock-complex@18700 {
+				#clock-cells = <1>;
+				compatible = "marvell,mv98dx3236-cpu-clock";
+				reg = <0x18700 0x24>, <0x1c054 0x10>;
+				clocks = <&coreclk 1>;
+			};
+
+			corediv-clock@18740 {
+				status = "disabled";
+			};
+
+			cpu-config@21000 {
+				compatible = "marvell,armada-xp-cpu-config";
+				reg = <0x21000 0x8>;
+			};
+
+			ethernet@70000 {
+				compatible = "marvell,armada-xp-neta";
+			};
+
+			ethernet@74000 {
+				compatible = "marvell,armada-xp-neta";
+			};
+
+			xor1: xor@f0800 {
+				compatible = "marvell,orion-xor";
+				reg = <0xf0800 0x100
+				       0xf0a00 0x100>;
+				clocks = <&gateclk 22>;
+				status = "okay";
+
+				xor10 {
+					interrupts = <51>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor11 {
+					interrupts = <52>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
+			};
+
+			nand_controller: nand@d0000 {
+				clocks = <&dfx_coredivclk 0>;
+			};
+
+			xor0: xor@f0900 {
+				compatible = "marvell,orion-xor";
+				reg = <0xF0900 0x100
+				       0xF0B00 0x100>;
+				clocks = <&gateclk 28>;
+				status = "okay";
+
+				xor00 {
+					interrupts = <94>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor01 {
+					interrupts = <95>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
+			};
+		};
+
+		dfx: dfx-server@ac000000 {
+			compatible = "marvell,dfx-server", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+                        thermal: thermal@f8078 {
+                                compatible = "marvell,armada380-thermal";
+                                reg = <0xf8078 0x4>, <0xf8074 0x4>;
+                                status = "okay";
+                        };
+
+			coreclk: mvebu-sar@f8204 {
+				compatible = "marvell,mv98dx3236-core-clock";
+				reg = <0xf8204 0x4>;
+				#clock-cells = <1>;
+			};
+
+			dfx_coredivclk: corediv-clock@f8268 {
+				compatible = "marvell,mv98dx3236-corediv-clock";
+				reg = <0xf8268 0xc>;
+				#clock-cells = <1>;
+				clocks = <&mainpll>;
+				clock-output-names = "nand";
+			};
+		};
+
+		switch: switch@a8000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+			pp0: packet-processor@0 {
+				compatible = "marvell,prestera-98dx3236", "marvell,prestera";
+				reg = <0 0x4000000>;
+				interrupts = <33>, <34>, <35>;
+				dfx = <&dfx>;
+			};
+		};
+	};
+
+	clocks {
+		/* 25 MHz reference crystal */
+		refclk: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+	};
+};
+
+&i2c0 {
+	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+	reg = <0x11000 0x100>;
+};
+
+&i2c1 {
+	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+	reg = <0x11100 0x100>;
+};
+
+&mpic {
+	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+};
+
+&rtc {
+	status = "disabled";
+};
+
+&timer {
+	compatible = "marvell,armada-xp-timer";
+	clocks = <&coreclk 2>, <&refclk>;
+	clock-names = "nbclk", "fixed";
+};
+
+&watchdog {
+	compatible = "marvell,armada-xp-wdt";
+	clocks = <&coreclk 2>, <&refclk>;
+	clock-names = "nbclk", "fixed";
+};
+
+&cpurst {
+	reg = <0x20800 0x20>;
+};
+
+&usb0 {
+	clocks = <&gateclk 18>;
+};
+
+&usb1 {
+	clocks = <&gateclk 19>;
+};
+
+&pinctrl {
+	compatible = "marvell,98dx3236-pinctrl";
+
+	nand_pins: nand-pins {
+		marvell,pins = "mpp20", "mpp21", "mpp22",
+			       "mpp23", "mpp24", "mpp25",
+			       "mpp26", "mpp27", "mpp28",
+			       "mpp29", "mpp30";
+		marvell,function = "dev";
+	};
+
+	nand_rb: nand-rb {
+		marvell,pins = "mpp19";
+		marvell,function = "nand";
+	};
+
+	spi0_pins: spi0-pins {
+		marvell,pins = "mpp0", "mpp1",
+			       "mpp2", "mpp3";
+		marvell,function = "spi0";
+	};
+};
+
+&spi0 {
+	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+	pinctrl-0 = <&spi0_pins>;
+	pinctrl-names = "default";
+};
+
+&sdio {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/armada-xp-98dx3336.dtsi b/arch/arm/dts/armada-xp-98dx3336.dtsi
new file mode 100644
index 000000000000..1d9d8a8ea60c
--- /dev/null
+++ b/arch/arm/dts/armada-xp-98dx3336.dtsi
@@ -0,0 +1,39 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Marvell 98dx3336 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp-98dx3236.dtsi"
+
+/ {
+	model = "Marvell 98DX3336 SoC";
+	compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
+
+	cpus {
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "marvell,sheeva-v7";
+			reg = <1>;
+			clocks = <&cpuclk 1>;
+			clock-latency = <1000000>;
+		};
+	};
+
+	soc {
+		internal-regs {
+			resume@20980 {
+				compatible = "marvell,98dx3336-resume-ctrl";
+				reg = <0x20980 0x10>;
+			};
+		};
+	};
+};
+
+&pp0 {
+	compatible = "marvell,prestera-98dx3336", "marvell,prestera";
+};
diff --git a/arch/arm/dts/armada-xp-98dx4251.dtsi b/arch/arm/dts/armada-xp-98dx4251.dtsi
new file mode 100644
index 000000000000..48ffdc72bfc7
--- /dev/null
+++ b/arch/arm/dts/armada-xp-98dx4251.dtsi
@@ -0,0 +1,54 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Marvell 98dx4521 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Contains definitions specific to the 98dx4521 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp-98dx3236.dtsi"
+
+/ {
+	model = "Marvell 98DX4251 SoC";
+	compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
+
+	cpus {
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "marvell,sheeva-v7";
+			reg = <1>;
+			clocks = <&cpuclk 1>;
+			clock-latency = <1000000>;
+		};
+	};
+
+	soc {
+		internal-regs {
+			resume@20980 {
+				compatible = "marvell,98dx3336-resume-ctrl";
+				reg = <0x20980 0x10>;
+			};
+		};
+	};
+};
+
+&sdio {
+	status = "okay";
+};
+
+&pinctrl {
+	compatible = "marvell,98dx4251-pinctrl";
+
+	sdio_pins: sdio-pins {
+		marvell,pins = "mpp5", "mpp6", "mpp7",
+			       "mpp8", "mpp9", "mpp10";
+		marvell,function = "sd0";
+	};
+};
+
+&pp0 {
+	compatible = "marvell,prestera-98dx4251", "marvell,prestera";
+	interrupts = <33>, <34>, <35>, <36>;
+};
diff --git a/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
new file mode 100644
index 000000000000..2daf83e655ac
--- /dev/null
+++ b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
@@ -0,0 +1,122 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for DB-XC3-24G4XG board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx3336.dtsi"
+
+/ {
+	model = "DB-XC3-24G4XG";
+	compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	aliases {
+		spi0 = &spi0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
+	};
+};
+
+&L2 {
+	arm,parity-enable;
+	marvell,ecc-enable;
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	/* Device Bus parameters are required */
+
+	/* Read parameters */
+	devbus,bus-width    = <16>;
+	devbus,turn-off-ps  = <60000>;
+	devbus,badr-skew-ps = <0>;
+	devbus,acc-first-ps = <124000>;
+	devbus,acc-next-ps  = <248000>;
+	devbus,rd-setup-ps  = <0>;
+	devbus,rd-hold-ps   = <0>;
+
+	/* Write parameters */
+	devbus,sync-enable = <0>;
+	devbus,wr-high-ps  = <60000>;
+	devbus,wr-low-ps   = <60000>;
+	devbus,ale-wr-ps   = <60000>;
+};
+
+&uart0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&nand_controller {
+	compatible="marvell,mvebu-pxa3xx-nand";
+	status = "okay";
+	label = "pxa3xx_nand-0";
+	nand-rb = <0>;
+	marvell,nand-keep-config;
+	nand-on-flash-bbt;
+	nand-ecc-strength = <4>;
+	nand-ecc-step-size = <512>;
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash", "jedec,spi-nor";
+		reg = <0>; /* Chip select 0 */
+		spi-max-frequency = <108000000>;
+		m25p,fast-read;
+
+		partition@u-boot {
+			reg = <0x00000000 0x00100000>;
+			label = "u-boot";
+		};
+		partition@u-boot-env {
+			reg = <0x00100000 0x00040000>;
+			label = "u-boot-env";
+		};
+		partition@unused {
+			reg = <0x00140000 0x00ec0000>;
+			label = "unused";
+		};
+
+	};
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 05aa2ade0499..938466615c66 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -152,6 +152,10 @@  config TARGET_X530
 	bool "Support Allied Telesis x530"
 	select 88F6820
 
+config TARGET_DB_XC3_24G4XG
+	bool "Support DB-XC3-24G4XG"
+	select 98DX3336
+
 endchoice
 
 config SYS_BOARD
@@ -170,6 +174,7 @@  config SYS_BOARD
 	default "theadorable" if TARGET_THEADORABLE
 	default "a38x" if TARGET_CONTROLCENTERDC
 	default "x530" if TARGET_X530
+	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 
 config SYS_CONFIG_NAME
 	default "clearfog" if TARGET_CLEARFOG
@@ -187,6 +192,7 @@  config SYS_CONFIG_NAME
 	default "turris_mox" if TARGET_TURRIS_MOX
 	default "controlcenterdc" if TARGET_CONTROLCENTERDC
 	default "x530" if TARGET_X530
+	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 
 config SYS_VENDOR
 	default "Marvell" if TARGET_DB_MV784MP_GP
@@ -195,6 +201,8 @@  config SYS_VENDOR
 	default "Marvell" if TARGET_DB_88F6820_GP
 	default "Marvell" if TARGET_DB_88F6820_AMC
 	default "Marvell" if TARGET_MVEBU_ARMADA_8K
+	default "Marvell" if TARGET_DB_XC3_24G4XG
+	default "Marvell" if TARGET_MVEBU_DB_88F7040
 	default "solidrun" if TARGET_CLEARFOG
 	default "kobol" if TARGET_HELIOS4
 	default "Synology" if TARGET_DS414
diff --git a/board/Marvell/db-xc3-24g4xg/MAINTAINERS b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
new file mode 100644
index 000000000000..94d4a901783b
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
@@ -0,0 +1,7 @@ 
+DB-XC3-24G4XG BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/Marvell/db-xc3-24g4xg/
+F:	include/configs/db-xc3-24g4xg.h
+F:	configs/db-xc3-24g4xg-amc_defconfig
+F:	arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
diff --git a/board/Marvell/db-xc3-24g4xg/Makefile b/board/Marvell/db-xc3-24g4xg/Makefile
new file mode 100644
index 000000000000..199837a84fe6
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/Makefile
@@ -0,0 +1,5 @@ 
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y	:= db-xc3-24g4xg.o
diff --git a/board/Marvell/db-xc3-24g4xg/README b/board/Marvell/db-xc3-24g4xg/README
new file mode 100644
index 000000000000..5e479b433e4d
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/README
@@ -0,0 +1,4 @@ 
+To generate binary.0 from Marvell's bin_hdr.elf use the following command
+
+    arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \
+       board/Marvell/db-xc3-24g4xg/binary.0
diff --git a/board/Marvell/db-xc3-24g4xg/binary.0 b/board/Marvell/db-xc3-24g4xg/binary.0
new file mode 100644
index 000000000000..8dd687286a00
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/binary.0
@@ -0,0 +1,11 @@ 
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
new file mode 100644
index 000000000000..428e3f611798
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
@@ -0,0 +1,71 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * These values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
+ */
+#define DB_DX_AC3_GPP_OUT_ENA_LOW	(~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
+					| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29)  | BIT(30)))
+#define DB_DX_AC3_GPP_OUT_ENA_MID	(~(0))
+#define DB_DX_AC3_GPP_OUT_VAL_LOW	(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
+					| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29)  | BIT(30))
+#define DB_DX_AC3_GPP_OUT_VAL_MID	0x0
+#define DB_DX_AC3_GPP_POL_LOW		0x0
+#define DB_DX_AC3_GPP_POL_MID		0x0
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x00142222, MVEBU_MPP_BASE + 0x00);
+	writel(0x11122000, MVEBU_MPP_BASE + 0x04);
+	writel(0x44444004, MVEBU_MPP_BASE + 0x08);
+	writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
+	writel(0x00000001, MVEBU_MPP_BASE + 0x10);
+
+	/* Set GPP Out value */
+	writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* Disable MBUS Err Prop - in order to avoid data aborts */
+	clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8));
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board: " CONFIG_SYS_BOARD "\n");
+
+	return 0;
+}
+#endif
diff --git a/board/Marvell/db-xc3-24g4xg/kwbimage.cfg b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
new file mode 100644
index 000000000000..b8bb7a6eb75b
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
@@ -0,0 +1,12 @@ 
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068
diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig
new file mode 100644
index 000000000000..0285ccaa365c
--- /dev/null
+++ b/configs/db-xc3-24g4xg_defconfig
@@ -0,0 +1,55 @@ 
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_DB_XC3_24G4XG=y
+CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_BLK=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_NAND=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h
new file mode 100644
index 000000000000..2638ff9d7577
--- /dev/null
+++ b/include/configs/db-xc3-24g4xg.h
@@ -0,0 +1,45 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_DB_XC3_24G4G_H
+#define _CONFIG_DB_XC3_24G4G_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_SYS_TCLK		200000000	/* 200MHz */
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		1000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+
+/* NAND */
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 96
+
+#endif /* _CONFIG_DB_XC3_24G4G_H */
diff --git a/tools/Makefile b/tools/Makefile
index 081383d7a790..463f165f9572 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -148,6 +148,10 @@  ifneq ($(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),)
 HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE
 endif
 
+ifneq ($(CONFIG_MSYS),)
+HOSTCFLAGS_kwbimage.o += -DCONFIG_MSYS
+endif
+
 # MXSImage needs LibSSL
 ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE),)
 HOSTLOADLIBES_mkimage += \
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index a88a3830c0c8..8d60dc001112 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1252,8 +1252,12 @@  static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
 		cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
 	main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
 	main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
+#ifdef CONFIG_MSYS
+	main_hdr->destaddr     = cpu_to_le32(params->addr);
+#else
 	main_hdr->destaddr     = cpu_to_le32(params->addr)
 				 - sizeof(image_header_t);
+#endif
 	main_hdr->execaddr     = cpu_to_le32(params->ep);
 	main_hdr->srcaddr      = cpu_to_le32(headersz);
 	main_hdr->ext          = hasext;