From patchwork Fri Feb 1 15:04:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1034811 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43rgRg5L1Dz9s4V for ; Sat, 2 Feb 2019 02:06:39 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 73191C21D8A; Fri, 1 Feb 2019 15:05:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1844AC21C27; Fri, 1 Feb 2019 15:05:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2CEC7C21DF3; Fri, 1 Feb 2019 15:05:20 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) by lists.denx.de (Postfix) with ESMTPS id 03D51C21C27 for ; Fri, 1 Feb 2019 15:05:16 +0000 (UTC) Received: from localhost.localdomain ([81.221.68.199]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0LkAKy-1hRgLu1kWQ-00cAOB; Fri, 01 Feb 2019 16:05:08 +0100 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Fri, 1 Feb 2019 16:04:51 +0100 Message-Id: <20190201150451.4818-4-marcel@ziswiler.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201150451.4818-1-marcel@ziswiler.com> References: <20190201150451.4818-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:Z6mYYdrFhxxVKdO2oZIoJGVVTqu+0M4RRo0g3/IO/2ojrtkqtOR HbGGQsAausbYUy3tBLloyoaa62hWxPmsCh0gC1auAeTP4RNiLcSemD5Wnduw+WQlKvu+FAE 79C63QElQzkfdC4UhSaXT+UIgzQdI+GOTj8ZQMJXSuIMq5dQuSNFrKGY1EbaF6kgqpvNtLv 1nysis2IlXmwMEauFsOcA== X-UI-Out-Filterresults: notjunk:1; V03:K0:NTA84ovG0mg=:bZEUewrsuT2sIr6CYgCt/K 02RGor2f0/xa9xbeIVZZo+CQq9SgdOlgy3Wf0nr01NYj/lRBVxShRJs44+cfSPpssmfvrmLgR Nr/ho1ZA1Oc0KfpUf6XDc4K4B1satS5lLgfxbOk9Xu2y7Dz2zk+8379MYzAyprhm07tnh1bVs yGxw/jzpIzLqjT444Rh3q7rmq5AN3qnzVMkx8CcGD4SrwnytW4ymXBfY5mmze+z7M0msXXZqB lrSIUmrk0P+4pNgbSdknEJ7FRwdQvohmNP97k2WsiLdxeqyCUKuxd0YFYRYYzKt8zc0WaqStA bz7kbsrn/uAWpu4K1tA85Tz2ZqqAesuzM9H4f0v3oxn0MiK7Y+17tXlboNfN4XqbSyoqJgYg/ REvmTn2Rz4eArsyhBbI6JaKg6Qs1pSrSO7lQ+czhcXCMSIjlWGRscudrj+ugDI1hrMAzSk1Ox 9Tg4HIBkTz4LJnilT8aA4j/vSBOL1KQMCfTa/aPseV2CK3LLHuPW3amealeLL/AlzMaimhNQd /KsPpxfC5j7z30T+T7aoi7AfPWvnYP4scQMxa5Im6urWzppbtF5nz2jgEfVjDvqTXN0kzwnJN Fuwfbok1lXvBPPqDlsN5VLbMU586JInyxBw1oRsTjlDtY4fKl/XZowIy15kpQy6WRp+r+aaD9 xScAdyts0IbUxG12DIkWtqwjU9IQw9cswNkqS0h0Sv1d7W5dq6dzF2qVnUZQgqUkqUm1xGIzk XUNqRPaLTq/DK8Om6ixMW79yYjz/E4rGPf009A== Cc: "NXP i.MX U-Boot Team" , Marcel Ziswiler , Max Krummenacher , Fabio Estevam Subject: [U-Boot] [PATCH v1 3/3] imx: cpu.c: give access to reset cause in spl X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Max Krummenacher This makes get_imx_reset_cause() accessible in SPL, but keeps the SRSR register content intact so that U-Boot proper can evaluated the reset_cause again should this be needed. Signed-off-by: Max Krummenacher Acked-by: Marcel Ziswiler --- arch/arm/mach-imx/cpu.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 80d9ff48a4..6b83f92662 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -25,19 +25,27 @@ #include #endif -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) static u32 reset_cause = -1; -static char *get_reset_cause(void) +u32 get_imx_reset_cause(void) { - u32 cause; struct src *src_regs = (struct src *)SRC_BASE_ADDR; - cause = readl(&src_regs->srsr); - writel(cause, &src_regs->srsr); - reset_cause = cause; + if (reset_cause == -1) { + reset_cause = readl(&src_regs->srsr); +/* preserve the value for U-Boot proper */ +#if !defined(CONFIG_SPL_BUILD) + writel(reset_cause, &src_regs->srsr); +#endif + } + + return reset_cause; +} - switch (cause) { +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) +static char *get_reset_cause(void) +{ + switch (get_imx_reset_cause()) { case 0x00001: case 0x00011: return "POR"; @@ -77,11 +85,6 @@ static char *get_reset_cause(void) return "unknown reset"; } } - -u32 get_imx_reset_cause(void) -{ - return reset_cause; -} #endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6)