From patchwork Mon Jan 21 11:32:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maciej Zagrabski X-Patchwork-Id: 1028692 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=grinn-global.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43jtRS4bbWz9sDB for ; Tue, 22 Jan 2019 00:57:56 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4A26DC21F62; Mon, 21 Jan 2019 13:57:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 68A73C21EE4; Mon, 21 Jan 2019 13:43:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C2D19C21DD7; Mon, 21 Jan 2019 11:32:47 +0000 (UTC) Received: from smtp.megiteam.pl (smtp.megiteam.pl [31.186.83.105]) by lists.denx.de (Postfix) with ESMTPS id 7E423C21DD4 for ; Mon, 21 Jan 2019 11:32:47 +0000 (UTC) Received: from [95.143.241.142] (helo=winston.grinn-global.com) by smtp.megiteam.pl with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.82) (envelope-from ) id 1glXor-0003wr-2P; Mon, 21 Jan 2019 12:32:46 +0100 From: Maciej Zagrabski To: u-boot@lists.denx.de Date: Mon, 21 Jan 2019 12:32:18 +0100 Message-Id: <20190121113218.10708-1-maciej.zagrabski@grinn-global.com> X-Mailer: git-send-email 2.11.0 X-Mailman-Approved-At: Mon, 21 Jan 2019 13:43:17 +0000 Cc: Maciej Zagrabski , Piotr Figlarek , Tom Rini Subject: [U-Boot] [RFC PATCH] am335x: Changes in DDR init procedure to Support Samsung K4B2G1646EBIH9 memory chip X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" K4B2G1646EBIH9 Samsung memory chip used now on chiliSOM requires refresh register REF CTRL to be initialized with large enough value, faster than it is implemented in `config_sdram` in ddr.c for am33xx, that mean before setting ZQ CTRL. Change should not interferee with already supported DDR chips cause refresh rate value is large enough to cover initialization, but it will finish during `udelay` below anyway. If this is not acceptable I can `ifdef` this line with config introduced in previous patch. Signed-off-by: Maciej Zagrabski --- arch/arm/mach-omap2/am33xx/ddr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index be6f4d72ccd..3684508bb1c 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -171,12 +171,13 @@ void config_sdram(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); #else if (regs->zq_config) { + /* Trigger initialization */ + writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); - /* Trigger initialization */ - writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); /* Wait 1ms because of L3 timeout error */ udelay(1000);