From patchwork Tue Dec 4 10:10:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 1007550 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=agner.ch Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=agner.ch header.i=@agner.ch header.b="MuE5zYFu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 438HjW3vFXz9s7W for ; Tue, 4 Dec 2018 21:12:31 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 10A3DC22161; Tue, 4 Dec 2018 10:11:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 70690C22131; Tue, 4 Dec 2018 10:10:29 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 77EC1C21D9A; Tue, 4 Dec 2018 10:10:26 +0000 (UTC) Received: from mail.kmu-office.ch (mail.kmu-office.ch [178.209.48.109]) by lists.denx.de (Postfix) with ESMTPS id 30A03C21DD9 for ; Tue, 4 Dec 2018 10:10:26 +0000 (UTC) Received: from trochilidae.toradex.int (unknown [46.140.72.82]) by mail.kmu-office.ch (Postfix) with ESMTPSA id D76DF5C15C3; Tue, 4 Dec 2018 11:10:25 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=agner.ch; s=dkim; t=1543918225; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=u0+jruFbPg40oDD1+KYBenxK2Ubzz/SdlG269WtEy3w=; b=MuE5zYFuVQF7uWCxGFRPkcVnR3OrwRtBNRIXxbULM7SLFIzHAT57c9HGbh0hs3VZOPxNYF B+xj+ERlO/VkeEAq7/wbpnoMxk+S1cbEtX5UgLGW7ssaF2++8Z9cdjDpot5sPYPTsptvAb XEy6Bx91f13ovqwa9lNz5J2E00vLbJU= From: Stefan Agner To: Stefano Babic , u-boot@lists.denx.de, lukma@denx.de Date: Tue, 4 Dec 2018 11:10:20 +0100 Message-Id: <20181204101021.22817-4-stefan@agner.ch> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181204101021.22817-1-stefan@agner.ch> References: <20181204101021.22817-1-stefan@agner.ch> MIME-Version: 1.0 Cc: mark.middleton@nxp.com, linux-imx@nxp.com, Stefan Agner Subject: [U-Boot] [PATCH v1 3/4] ARM: vf610: ddrmc: fix initialization completion detection X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Agner The CR80 register has multiple interrupt bits, the code is supposed to check bit 8 but instead uses a logical and. In most cases this probably did not affect real operations since at that stage typically none of the other bits are set. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- arch/arm/include/asm/arch-vf610/imx-regs.h | 3 ++- arch/arm/mach-imx/ddrmc-vf610.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index b7374bfb8f..f71fbf4e73 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -200,7 +200,8 @@ #define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) #define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) -#define DDRMC_CR82_INT_MASK 0x10000000 +#define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8) +#define DDRMC_CR82_INT_MASK (1 << 28) #define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24) #define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c index 3d7da1c25e..d121a53898 100644 --- a/arch/arm/mach-imx/ddrmc-vf610.c +++ b/arch/arm/mach-imx/ddrmc-vf610.c @@ -231,6 +231,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, /* all inits done, start the DDR controller */ writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); - while (!(readl(&ddrmr->cr[80]) && 0x100)) + while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE)) udelay(10); + writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]); }