From patchwork Fri Nov 30 19:32:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Muellner X-Patchwork-Id: 1006217 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=theobroma-systems.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4367X863vHz9sB7 for ; Sat, 1 Dec 2018 08:56:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D0112C225BF; Fri, 30 Nov 2018 21:56:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 21B50C225A5; Fri, 30 Nov 2018 21:52:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8F32AC2203F; Fri, 30 Nov 2018 19:33:21 +0000 (UTC) Received: from mail.theobroma-systems.com (vegas.theobroma-systems.com [144.76.126.164]) by lists.denx.de (Postfix) with ESMTPS id 3D851C22028 for ; Fri, 30 Nov 2018 19:33:21 +0000 (UTC) Received: from [86.59.122.178] (port=40074 helo=purcell.lan) by mail.theobroma-systems.com with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1gSoXP-0006d9-Dh; Fri, 30 Nov 2018 20:33:19 +0100 From: Christoph Muellner To: Philipp Tomsich , Simon Glass , Albert Aribaud , Mark Kettenis Date: Fri, 30 Nov 2018 20:32:48 +0100 Message-Id: <20181130193248.27738-1-christoph.muellner@theobroma-systems.com> X-Mailer: git-send-email 2.11.0 X-Mailman-Approved-At: Fri, 30 Nov 2018 21:52:02 +0000 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2] rockchip: rk3399: Initialize CPU B clock. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz. This decreases the boot time of Linux 4.19 by about 8%. The 600 MHz are inspired by the 600 MHz used for LPLL initialization (came in with commit 9f636a249c1). Tested on RK3399-Q7 on Haikou base board. Changes since v1: * Set clk_core_b parent to BPLL instead of LPLL. Kudos to Mark Kettenis for spotting this. Signed-off-by: Christoph Muellner --- arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 22 +++++-- drivers/clk/rockchip/clk_rk3399.c | 79 ++++++++++++++++++++++--- 2 files changed, 88 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index b18de9f7c2e..15eeb9c4407 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -69,16 +69,21 @@ check_member(rk3399_cru, sdio1_con[1], 0x594); #define MHz 1000000 #define KHz 1000 #define OSC_HZ (24*MHz) -#define APLL_HZ (600*MHz) +#define LPLL_HZ (600*MHz) +#define BPLL_HZ (600*MHz) #define GPLL_HZ (594*MHz) #define CPLL_HZ (384*MHz) #define PPLL_HZ (676*MHz) #define PMU_PCLK_HZ (48*MHz) -#define ACLKM_CORE_HZ (300*MHz) -#define ATCLK_CORE_HZ (300*MHz) -#define PCLK_DBG_HZ (100*MHz) +#define ACLKM_CORE_L_HZ (300*MHz) +#define ATCLK_CORE_L_HZ (300*MHz) +#define PCLK_DBG_L_HZ (100*MHz) + +#define ACLKM_CORE_B_HZ (300*MHz) +#define ATCLK_CORE_B_HZ (300*MHz) +#define PCLK_DBG_B_HZ (100*MHz) #define PERIHP_ACLK_HZ (148500*KHz) #define PERIHP_HCLK_HZ (148500*KHz) @@ -98,4 +103,13 @@ enum apll_l_frequencies { APLL_L_600_MHZ, }; +enum apll_b_frequencies { + APLL_B_600_MHZ, +}; + +void rk3399_configure_cpu_l(struct rk3399_cru *cru, + enum apll_l_frequencies apll_l_freq); +void rk3399_configure_cpu_b(struct rk3399_cru *cru, + enum apll_b_frequencies apll_b_freq); + #endif /* __ASM_ARCH_CRU_RK3399_H_ */ diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 26faf88116b..198914b0676 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -61,6 +61,11 @@ static const struct pll_div *apll_l_cfgs[] = { [APLL_L_600_MHZ] = &apll_l_600_cfg, }; +static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div *apll_b_cfgs[] = { + [APLL_B_600_MHZ] = &apll_b_600_cfg, +}; + enum { /* PLL_CON0 */ PLL_FBDIV_MASK = 0xfff, @@ -128,6 +133,24 @@ enum { ATCLK_CORE_L_DIV_SHIFT = 0, ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT, + /* CLKSEL_CON2 */ + ACLKM_CORE_B_DIV_CON_SHIFT = 8, + ACLKM_CORE_B_DIV_CON_MASK = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT, + CLK_CORE_B_PLL_SEL_SHIFT = 6, + CLK_CORE_B_PLL_SEL_MASK = 3 << CLK_CORE_B_PLL_SEL_SHIFT, + CLK_CORE_B_PLL_SEL_ALPLL = 0x0, + CLK_CORE_B_PLL_SEL_ABPLL = 0x1, + CLK_CORE_B_PLL_SEL_DPLL = 0x10, + CLK_CORE_B_PLL_SEL_GPLL = 0x11, + CLK_CORE_B_DIV_MASK = 0x1f, + CLK_CORE_B_DIV_SHIFT = 0, + + /* CLKSEL_CON3 */ + PCLK_DBG_B_DIV_SHIFT = 0x8, + PCLK_DBG_B_DIV_MASK = 0x1f << PCLK_DBG_B_DIV_SHIFT, + ATCLK_CORE_B_DIV_SHIFT = 0, + ATCLK_CORE_B_DIV_MASK = 0x1f << ATCLK_CORE_B_DIV_SHIFT, + /* CLKSEL_CON14 */ PCLK_PERIHP_DIV_CON_SHIFT = 12, PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, @@ -395,25 +418,26 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return 0; } -void rk3399_configure_cpu(struct rk3399_cru *cru, - enum apll_l_frequencies apll_l_freq) +void rk3399_configure_cpu_l(struct rk3399_cru *cru, + enum apll_l_frequencies apll_l_freq) { u32 aclkm_div; u32 pclk_dbg_div; u32 atclk_div; + /* Setup cluster L */ rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]); - aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1; - assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ && + aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1; + assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ && aclkm_div < 0x1f); - pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1; - assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ && + pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1; + assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ && pclk_dbg_div < 0x1f); - atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1; - assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ && + atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1; + assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ && atclk_div < 0x1f); rk_clrsetreg(&cru->clksel_con[0], @@ -428,6 +452,42 @@ void rk3399_configure_cpu(struct rk3399_cru *cru, pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT | atclk_div << ATCLK_CORE_L_DIV_SHIFT); } + +void rk3399_configure_cpu_b(struct rk3399_cru *cru, + enum apll_b_frequencies apll_b_freq) +{ + u32 aclkm_div; + u32 pclk_dbg_div; + u32 atclk_div; + + /* Setup cluster B */ + rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]); + + aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1; + assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ && + aclkm_div < 0x1f); + + pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1; + assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ && + pclk_dbg_div < 0x1f); + + atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1; + assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ && + atclk_div < 0x1f); + + rk_clrsetreg(&cru->clksel_con[2], + ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK | + CLK_CORE_B_DIV_MASK, + aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT | + CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT | + 0 << CLK_CORE_B_DIV_SHIFT); + + rk_clrsetreg(&cru->clksel_con[3], + PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK, + pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT | + atclk_div << ATCLK_CORE_B_DIV_SHIFT); +} + #define I2C_CLK_REG_MASK(bus) \ (I2C_DIV_CON_MASK << \ CLK_I2C ##bus## _DIV_CON_SHIFT | \ @@ -1026,7 +1086,8 @@ static void rkclk_init(struct rk3399_cru *cru) u32 hclk_div; u32 pclk_div; - rk3399_configure_cpu(cru, APLL_L_600_MHZ); + rk3399_configure_cpu_l(cru, APLL_L_600_MHZ); + rk3399_configure_cpu_b(cru, APLL_B_600_MHZ); /* * some cru registers changed by bootrom, we'd better reset them to * reset/default values described in TRM to avoid confusion in kernel.