From patchwork Thu Nov 22 23:37:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Weidinger X-Patchwork-Id: 1002070 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=tum.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=tum.de header.i=@tum.de header.b="lChzAOhE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 431G974pP3z9s0n for ; Fri, 23 Nov 2018 10:38:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5E96DC221BA; Thu, 22 Nov 2018 23:38:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7E7E7C221BA; Thu, 22 Nov 2018 23:38:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 62F2CC221BA; Thu, 22 Nov 2018 23:38:29 +0000 (UTC) Received: from postout1.mail.lrz.de (postout1.mail.lrz.de [129.187.255.137]) by lists.denx.de (Postfix) with ESMTPS id F0A77C2219C for ; Thu, 22 Nov 2018 23:38:28 +0000 (UTC) Received: from lxmhs51.srv.lrz.de (localhost [127.0.0.1]) by postout1.mail.lrz.de (Postfix) with ESMTP id 431G901YHvzybd; Fri, 23 Nov 2018 00:38:28 +0100 (CET) Authentication-Results: postout.lrz.de (amavisd-new); dkim=pass (2048-bit key) reason="pass (just generated, assumed good)" header.d=tum.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tum.de; h= content-transfer-encoding:mime-version:references:in-reply-to :x-mailer:message-id:date:date:subject:subject:from:from :received:received; s=postout; t=1542929907; bh=8tBo1JTYdwl+6WTI cRhgwbZwel6BVIU3lONNLIb1xTY=; b=lChzAOhEuZh8k/9Y/qZdmtCVwGZewiVZ rsPWhgjndQXe5LKiPgsTD9ZNeNL7No9ug9x5bkdui+lESzOh4qd5MdKyJqAjuROx 74gS+QteZaRuaNLGp1OcnsEgyMTP6zk+KD6A+rq3CCK3juo05t/8aiiwJ68gbZ8m g5KViHio+NBUrwDQ6gN8+7x/AaWR8JgWkng6DE6hijJpgsLAgs9xlZhOv5SvQoVz js7/7T+ftqTZA2L/kAioVpIjWs7gZGLUA8MCXrzx07e9TSBRYz8/riuB+j2pOurd EaRPZbOPLJr/pAdigcJHnZUBkgl5mTjsBc7N/l67EA7QQYqcZJX5tQ== X-Virus-Scanned: by amavisd-new at lrz.de in lxmhs51.srv.lrz.de Received: from postout1.mail.lrz.de ([127.0.0.1]) by lxmhs51.srv.lrz.de (lxmhs51.srv.lrz.de [127.0.0.1]) (amavisd-new, port 20024) with LMTP id bXFFp54XqDc8; Fri, 23 Nov 2018 00:38:27 +0100 (CET) Received: from thanatos.HOMENET (p200300C4EF292300C96FABF1326A3B68.dip0.t-ipconnect.de [IPv6:2003:c4:ef29:2300:c96f:abf1:326a:3b68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by postout1.mail.lrz.de (Postfix) with ESMTPSA id 431G8z2yX5zybF; Fri, 23 Nov 2018 00:38:27 +0100 (CET) From: Alexander Weidinger To: u-boot@lists.denx.de Date: Fri, 23 Nov 2018 00:37:48 +0100 Message-Id: <20181122233748.25233-1-alexander.weidinger@tum.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181115220742.2530-1-alexander.weidinger@tum.de> References: <20181115220742.2530-1-alexander.weidinger@tum.de> MIME-Version: 1.0 Cc: joe.hershberger@ni.com, Icenowy Zheng Subject: [U-Boot] [PATCH v2] sun8i_emac: add support for setting EMAC TX/RX delay X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Icenowy Zheng Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng Reviewed-by: Jagan Teki --- Changes for v2: - Make use of `dev_get_platdata` instead of type casting - Patch 2/2 is superseded [ commit 1b39a1834ed182bbd8036a5cd74a9ea111fa4691 ] drivers/net/sun8i_emac.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 3ba3a1ff8b..c9798445c7 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -60,6 +60,10 @@ #define SC_ETCS_MASK GENMASK(1, 0) #define SC_ETCS_EXT_GMII 0x1 #define SC_ETCS_INT_GMII 0x2 +#define SC_ETXDC_MASK GENMASK(12, 10) +#define SC_ETXDC_OFFSET 10 +#define SC_ERXDC_MASK GENMASK(9, 5) +#define SC_ERXDC_OFFSET 5 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) @@ -140,6 +144,8 @@ struct emac_eth_dev { struct sun8i_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; + int tx_delay_ps; + int rx_delay_ps; }; @@ -273,7 +279,8 @@ static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg) return 0; } -static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) +static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + struct emac_eth_dev *priv) { int ret; u32 reg; @@ -312,6 +319,14 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) return -EINVAL; } + if (pdata->tx_delay_ps) + reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET) + & SC_ETXDC_MASK; + + if (pdata->rx_delay_ps) + reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET) + & SC_ERXDC_MASK; + writel(reg, priv->sysctl_reg + 0x30); return 0; @@ -784,13 +799,14 @@ static void sun8i_emac_eth_stop(struct udevice *dev) static int sun8i_emac_eth_probe(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_platdata(dev); + struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); + struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; struct emac_eth_dev *priv = dev_get_priv(dev); priv->mac_reg = (void *)pdata->iobase; sun8i_emac_board_setup(priv); - sun8i_emac_set_syscon(priv); + sun8i_emac_set_syscon(sun8i_pdata, priv); sun8i_mdio_init(dev->name, dev); priv->bus = miiphy_get_dev_by_name(dev->name); @@ -891,6 +907,18 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) if (!priv->use_internal_phy) parse_phy_pins(dev); + sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node, + "allwinner,tx-delay-ps", 0); + if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700) + printf("%s: Invalid TX delay value %d\n", __func__, + sun8i_pdata->tx_delay_ps); + + sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node, + "allwinner,rx-delay-ps", 0); + if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100) + printf("%s: Invalid RX delay value %d\n", __func__, + sun8i_pdata->rx_delay_ps); + #ifdef CONFIG_DM_GPIO if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "snps,reset-active-low"))