From patchwork Thu Nov 22 10:26:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 1001672 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430wr84cG3z9rxp for ; Thu, 22 Nov 2018 21:37:44 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 577AEC21EF2; Thu, 22 Nov 2018 10:32:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2909BC21FF6; Thu, 22 Nov 2018 10:28:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A3019C21F0C; Thu, 22 Nov 2018 10:27:45 +0000 (UTC) Received: from mail-edgeKA27.fraunhofer.de (mail-edgeka27.fraunhofer.de [153.96.1.27]) by lists.denx.de (Postfix) with ESMTPS id 5DB8DC21F29 for ; Thu, 22 Nov 2018 10:27:42 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2H4AAAO4PJb/xwBYJliGwEBAQEDAQEBBwMBAQGBZYFbKYFWOYxvix2LFJApDYRsAoNuIjgSAQMBAQIBAQICAmkcDIU+BnkQUSE2Bg4FgyGBagMUAah8h3YNghkJAYdQhCuBVz+BEAGFaIJ1hQ4CiSmWGC4HAoERgQkEi16DIAsYiViHJY5BiVWBXSKBVTMaJIM7gz0BAYJCilo+ATIBjlsBAQ X-IPAS-Result: A2H4AAAO4PJb/xwBYJliGwEBAQEDAQEBBwMBAQGBZYFbKYFWOYxvix2LFJApDYRsAoNuIjgSAQMBAQIBAQICAmkcDIU+BnkQUSE2Bg4FgyGBagMUAah8h3YNghkJAYdQhCuBVz+BEAGFaIJ1hQ4CiSmWGC4HAoERgQkEi16DIAsYiViHJY5BiVWBXSKBVTMaJIM7gz0BAYJCilo+ATIBjlsBAQ X-IronPort-AV: E=Sophos;i="5.56,253,1539640800"; d="scan'208";a="12041320" Received: from mail-mtaka28.fraunhofer.de ([153.96.1.28]) by mail-edgeKA27.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2018 11:27:43 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0C4AgDN3/JbfRBhWMBiHAEBAQQBAQcEAQGBZYFbgV4hOYxvljGQKQ2EbAKEDzgSAQMBAQIBAQIUAQEWOiMMhT0DA3kQUSE2Bg4FgyGBagMVqHuHdg2CGQkBh1CGAj+BEAGFaIJ1hQ4CiSmWGC4HAoERgQkEi16DIAsYiViHJY5BiVWBXSCBVjMaJIM7gz0BAYJCilo+AzABjlsBAQ X-IronPort-AV: E=Sophos;i="5.56,253,1539640800"; d="scan'208";a="19172008" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP11EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA28.fraunhofer.de with ESMTP/TLS/AES256-SHA; 22 Nov 2018 11:27:42 +0100 Received: from muc-nb-035.aisec.fraunhofer.de (10.80.233.50) by FGDEMUCIMP11EXC.ads.fraunhofer.de (10.80.232.42) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 22 Nov 2018 11:27:41 +0100 From: Lukas Auer To: Date: Thu, 22 Nov 2018 11:26:28 +0100 Message-ID: <20181122102637.17361-20-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181122102637.17361-1-lukas.auer@aisec.fraunhofer.de> References: <20181122102637.17361-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24238.005 X-TM-AS-Result: No--3.397900-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Greentime Hu Subject: [U-Boot] [PATCH v4 19/28] riscv: do not blindly modify the mstatus CSR X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The mstatus CSR includes WPRI (writes preserve values, reads ignore values) fields and must therefore not be set to zero without preserving these fields. It is not apparent why mstatus is set to zero here since it is not required for U-Boot to run. Remove it. This instruction and others encode zero as an immediate. RISC-V has the zero register for this purpose. Replace the immediates with the zero register. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v4: None Changes in v3: None Changes in v2: None arch/riscv/cpu/start.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index c313477ae0..b01ea6e224 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -38,8 +38,9 @@ _start: SREG a2, 0(t0) la t0, trap_entry csrw mtvec, t0 - csrwi mstatus, 0 - csrwi mie, 0 + + /* mask all interrupts */ + csrw mie, zero /* * Set stackpointer in internal/ex RAM to call board_init_f @@ -160,11 +161,10 @@ clear_bss: add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ - li t2, 0x00000000 /* clear */ beq t0, t1, call_board_init_r clbss_l: - SREG t2, 0(t0) /* clear loop... */ + SREG zero, 0(t0) /* clear loop... */ addi t0, t0, REGBYTES bne t0, t1, clbss_l