From patchwork Wed Nov 21 10:43:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 1001062 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="CkCyNFnw"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430K7M6vrmz9s0t for ; Wed, 21 Nov 2018 21:48:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8B248C22276; Wed, 21 Nov 2018 10:48:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8A239C22275; Wed, 21 Nov 2018 10:47:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C1D4EC22278; Wed, 21 Nov 2018 10:43:24 +0000 (UTC) Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50075.outbound.protection.outlook.com [40.107.5.75]) by lists.denx.de (Postfix) with ESMTPS id 7B6C0C22299 for ; Wed, 21 Nov 2018 10:43:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7+U7+dPAr5R3H74y3nwazn7QFrfQA6z8FcAwOdDsefE=; b=CkCyNFnwn+lH7egNcH0t8IFS8oEq8tp7ClmQrJM0z7agzuyQINR1ifmQOvVr9Or6pGLELsB7uaw+TPcnWjry+zyZ023HTkEyKs8kDw32kfSWw1bq+xa7UunINCdudnAbhV5I9Hb1MXhDP6zh7ZLQbFPkiFV/LnbhSSoeu7tm/hU= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.2.80) by AM6PR04MB4422.eurprd04.prod.outlook.com (20.177.39.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1294.26; Wed, 21 Nov 2018 10:43:15 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::29b5:b3ed:3854:cf1c%4]) with mapi id 15.20.1339.027; Wed, 21 Nov 2018 10:43:15 +0000 From: "Z.q. Hou" To: "u-boot@lists.denx.de" , "albert.u.boot@aribaud.net" , Priyanka Jain , York Sun , "sriram.dash@nxp.com" , "yamada.masahiro@socionext.com" , Prabhakar Kushwaha , Mingkai Hu , "M.h. Lian" Thread-Topic: [PATCHv2 5/8] pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Thread-Index: AQHUgYcBDQJ+0nqszUiHI9HADy4mkg== Date: Wed, 21 Nov 2018 10:43:15 +0000 Message-ID: <20181121104322.32839-6-Zhiqiang.Hou@nxp.com> References: <20181121104322.32839-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20181121104322.32839-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK0P153CA0022.APCP153.PROD.OUTLOOK.COM (2603:1096:203:18::34) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:aa::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB4422; 6:1GeEnzeEGAJHx/QRYFm686QplLzuq2jAxJyjXqVnzEf/eX8bdR+mDInG1YGGlAFQx4wLMlmXebBNb3XJIlhOfhHt7Qm4UiAv3Kqw8XaeAi+ZQl6eon0nHu4Bl9hztnjf/LNB5aDo4EedqyzbDcWrXtYSR68zpRNo+67Z5vdyMFMHWlpq4tyi2TaHbIpjhcX3SARMtD9OLVpypQJvFbC6YhIZAY0qo+TZAoIG1XWCXOeWP8hfFRzrBLPvYKU/198wyHnFGboTDRYiAhztNCnq4H02NeMfRzosFabV4hbODhqPiEMw2+A/aHst3MfDvdVN0JMwhZuE0uUTjJs4sn+kBPB61CKe1AQEbY07EUHq8ylwkvDiuoqdcHXNT5CHd3Pi1pGMNbbvRSgSTWBGr2KM6dWh5joCcHidlUh3GvEhDy3siUiY7qMScd7ONN4ulmvUMmirM/KqMgdrPm2IimfoaQ==; 5:0Dw5MpBWmH6qPvbOTi8xrCyU9t1Xr1qWzvAXbrLt6kA0HTYChUlAbT7lG4vnGVA6rCwH/M0YKRIS0nOBR2trMuyVM3e7k05d4GaTWQ5kwhyQHLwFqiCDgYWW196BlJPVfNkZxhAcltXMjWym4utzr6He6QpYuORuF1Cx8rN6l/c=; 7:OT9oXpceMblxzFCpWBqfVvqTLS6lrS3h8hG5Gdz6+uL2nNSY3x+Lg5MIPZnGzrCm5yCQgrfnmwnXlgtIyhH6pvEGGzLkMl2IHu1YCE6xfs81QVFdnkhSJjS01NzZr3l36wiETw1mzt1m5V1uNhMPLg== x-ms-office365-filtering-correlation-id: 9b28a623-d8c3-4050-0c6a-08d64f9e2437 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB4422; x-ms-traffictypediagnostic: AM6PR04MB4422: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(185117386973197)(85827821059158); x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(10201501046)(3002001)(3231442)(944501410)(52105112)(93006095)(93001095)(6055026)(148016)(149066)(150057)(6041310)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123560045)(201708071742011)(7699051)(76991095); SRVR:AM6PR04MB4422; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4422; x-forefront-prvs: 08635C03D4 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(396003)(376002)(346002)(136003)(199004)(189003)(476003)(2616005)(71200400001)(6486002)(446003)(486006)(3846002)(105586002)(106356001)(71190400001)(6116002)(68736007)(6436002)(186003)(102836004)(52116002)(7736002)(6506007)(2201001)(97736004)(386003)(26005)(2501003)(2900100001)(86362001)(76176011)(11346002)(110136005)(305945005)(2906002)(6636002)(99286004)(256004)(66066001)(25786009)(14444005)(478600001)(4326008)(6512007)(8676002)(53936002)(5660300001)(1076002)(81156014)(81166006)(8936002)(14454004)(316002)(36756003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4422; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: egzt0wELEYOgFtIQo+XOeRjNrVQzP18Nb6KIgXB2mP+JsMeGVAxgAStAeg9Z6zNEO7q2FQYPkNkFJe9eyvuwMINLGumSd6yOO1DGSCK9XXAoKn3ra3mdZ423fBDTbwbSzh6TmjxLUPSsYiXdRKn/wpsBrlVF0FNHnR/PIRFqJN6ee31guuqf+Pvka+Dn96fUlrsG2TICh8tzmwsFTUZMWm5vi6z7qc9NL0My6rOFW94F+XnTvEMDkp34iAM6vH4pXW0KjVsSjiWVIdTVH3WCwATUOTIVTy0TVQA0o8eWOS8uoAF06QLz3N+g+gh53ApmFqjNr5Kkh1qN9tz0YGwNL+pzUWOKH52R5W6oqbtMCaA= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9b28a623-d8c3-4050-0c6a-08d64f9e2437 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Nov 2018 10:43:15.3018 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4422 Cc: "Z.q. Hou" Subject: [U-Boot] [PATCHv2 5/8] pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Hou Zhiqiang Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang --- V2: - Changed the name of .c file, functions and data structures accrodingly. drivers/pci/Makefile | 3 +- drivers/pci/pcie_layerscape_gen4.c | 5 - drivers/pci/pcie_layerscape_gen4_fixup.c | 234 +++++++++++++++++++++++ 3 files changed, 236 insertions(+), 6 deletions(-) create mode 100644 drivers/pci/pcie_layerscape_gen4_fixup.c diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 7f585aad55..8ee828af6d 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o -obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o +obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \ + pcie_layerscape_gen4_fixup.o obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 19e391b50a..9e43ef5409 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -602,8 +602,3 @@ U_BOOT_DRIVER(pcie_layerscape_gen4) = { .probe = ls_pcie_g4_probe, .priv_auto_alloc_size = sizeof(struct ls_pcie_g4), }; - -/* No any fixup so far */ -void ft_pci_setup(void *blob, bd_t *bd) -{ -} diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c new file mode 100644 index 0000000000..c044e3263f --- /dev/null +++ b/drivers/pci/pcie_layerscape_gen4_fixup.c @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018 NXP + * + * PCIe Gen4 driver for NXP Layerscape SoCs + * Author: Hou Zhiqiang + * + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_OF_BOARD_SETUP +#include +#include +#ifdef CONFIG_ARM +#include +#endif +#include "pcie_layerscape_gen4.h" + +#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) +/* + * Return next available LUT index. + */ +static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie) +{ + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) + return pcie->next_lut_index++; + else + return -ENOSPC; /* LUT is full */ +} + +/* returns the next available streamid for pcie, -errno if failed */ +static int ls_pcie_g4_next_streamid(struct ls_pcie_g4 *pcie) +{ + int stream_id = pcie->stream_id_cur; + + if (stream_id > FSL_PEX_STREAM_ID_NUM) + return -EINVAL; + + pcie->stream_id_cur++; + + return stream_id | ((pcie->idx + 1) << 11); +} + +/* + * Program a single LUT entry + */ +static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index, + u32 devid, u32 streamid) +{ + /* leave mask as all zeroes, want to match all bits */ + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index)); + lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index)); +} + +/* + * An msi-map is a property to be added to the pci controller + * node. It is a table, where each entry consists of 4 fields + * e.g.: + * + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count] + * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>; + */ +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie_g4 *pcie, + u32 devid, u32 streamid) +{ + u32 *prop; + u32 phandle; + int nodeoff; + +#ifdef CONFIG_FSL_PCIE_COMPAT + nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT, + pcie->ccsr_res.start); +#else +#error "No CONFIG_FSL_PCIE_COMPAT defined" +#endif + if (nodeoff < 0) { + debug("%s: ERROR: failed to find pcie compatiable\n", + __func__); + return; + } + + /* get phandle to MSI controller */ + prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0); + if (!prop) { + debug("\n%s: ERROR: missing msi-parent: PCIe%d\n", + __func__, pcie->idx); + return; + } + phandle = fdt32_to_cpu(*prop); + + /* set one msi-map row */ + fdt_appendprop_u32(blob, nodeoff, "msi-map", devid); + fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle); + fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid); + fdt_appendprop_u32(blob, nodeoff, "msi-map", 1); +} + +/* + * An iommu-map is a property to be added to the pci controller + * node. It is a table, where each entry consists of 4 fields + * e.g.: + * + * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count] + * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>; + */ +static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie_g4 *pcie, + u32 devid, u32 streamid) +{ + u32 *prop; + u32 iommu_map[4]; + int nodeoff; + int lenp; + +#ifdef CONFIG_FSL_PCIE_COMPAT + nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT, + pcie->ccsr_res.start); +#else +#error "No CONFIG_FSL_PCIE_COMPAT defined" +#endif + if (nodeoff < 0) { + debug("%s: ERROR: failed to find pcie compatiable\n", + __func__); + return; + } + + /* get phandle to iommu controller */ + prop = fdt_getprop_w(blob, nodeoff, "iommu-map", &lenp); + if (!prop) { + debug("\n%s: ERROR: missing iommu-map: PCIe%d\n", + __func__, pcie->idx); + return; + } + + /* set iommu-map row */ + iommu_map[0] = cpu_to_fdt32(devid); + iommu_map[1] = *++prop; + iommu_map[2] = cpu_to_fdt32(streamid); + iommu_map[3] = cpu_to_fdt32(1); + + if (devid == 0) { + fdt_setprop_inplace(blob, nodeoff, "iommu-map", + iommu_map, 16); + } else { + fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16); + } +} + +static void fdt_fixup_pcie(void *blob) +{ + struct udevice *dev, *bus; + struct ls_pcie_g4 *pcie; + int streamid; + int index; + pci_dev_t bdf; + + /* Scan all known buses */ + for (pci_find_first_device(&dev); + dev; + pci_find_next_device(&dev)) { + for (bus = dev; device_is_on_pci_bus(bus);) + bus = bus->parent; + pcie = dev_get_priv(bus); + + streamid = ls_pcie_g4_next_streamid(pcie); + if (streamid < 0) { + debug("ERROR: no stream ids free\n"); + continue; + } + + index = ls_pcie_g4_next_lut_index(pcie); + if (index < 0) { + debug("ERROR: no LUT indexes free\n"); + continue; + } + + /* the DT fixup must be relative to the hose first_busno */ + bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0); + /* map PCI b.d.f to streamID in LUT */ + ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, + streamid); + /* update msi-map in device tree */ + fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, + streamid); + /* update iommu-map in device tree */ + fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8, + streamid); + } +} +#endif + +static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie) +{ + int off; + +#ifdef CONFIG_FSL_PCIE_COMPAT + off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT, + pcie->ccsr_res.start); +#else +#error "No CONFIG_FSL_PCIE_COMPAT defined" +#endif + if (off < 0) { + debug("%s: ERROR: failed to find pcie compatiable\n", + __func__); + return; + } + + if (pcie->enabled) + fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0); + else + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +} + +/* Fixup Kernel DT for PCIe */ +void ft_pci_setup(void *blob, bd_t *bd) +{ + struct ls_pcie_g4 *pcie; + + list_for_each_entry(pcie, &ls_pcie_g4_list, list) + ft_pcie_layerscape_gen4_setup(blob, pcie); + +#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) + fdt_fixup_pcie(blob); +#endif +} + +#else /* !CONFIG_OF_BOARD_SETUP */ +void ft_pci_setup(void *blob, bd_t *bd) +{ +} +#endif