From patchwork Fri Nov 9 12:59:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 995489 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42s0hn2sztz9s1x for ; Sat, 10 Nov 2018 00:03:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 05F0FC220C7; Fri, 9 Nov 2018 13:02:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0D382C22593; Fri, 9 Nov 2018 13:00:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AB95AC22539; Fri, 9 Nov 2018 13:00:13 +0000 (UTC) Received: from mail-edgeS23.fraunhofer.de (mail-edges23.fraunhofer.de [153.97.7.23]) by lists.denx.de (Postfix) with ESMTPS id C8B28C22577 for ; Fri, 9 Nov 2018 13:00:08 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2EGAAAmhOVb/xoHYZlcCBoBAQEBAQIBAQEBBwIBAQEBgVEFAQEBAQsBggNmcDmHQoROX49VAYZXji4UgWYNG4EVgzwCgyIiNA0NAQMBAQIBAQICAmkcDIQfXz4GeRBRITYGDgWDIQGBaQMUAakFg3GECQ2CGQkBh0iEKoFYP4EQAYVogWEMFoYAAp8eLgcCgRGBBwSEV4Z7gyALGIlPhx+OJYYLAYNAgUM5gVUzGiSDOwmCHheBc4FQilo+ATIBjUMBAQ X-IPAS-Result: A2EGAAAmhOVb/xoHYZlcCBoBAQEBAQIBAQEBBwIBAQEBgVEFAQEBAQsBggNmcDmHQoROX49VAYZXji4UgWYNG4EVgzwCgyIiNA0NAQMBAQIBAQICAmkcDIQfXz4GeRBRITYGDgWDIQGBaQMUAakFg3GECQ2CGQkBh0iEKoFYP4EQAYVogWEMFoYAAp8eLgcCgRGBBwSEV4Z7gyALGIlPhx+OJYYLAYNAgUM5gVUzGiSDOwmCHheBc4FQilo+ATIBjUMBAQ X-IronPort-AV: E=Sophos;i="5.54,483,1534802400"; d="scan'208";a="7622505" Received: from mail-mtas26.fraunhofer.de ([153.97.7.26]) by mail-edgeS23.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Nov 2018 14:00:07 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0ALAADxg+Vb/xBhWMBcCBsBAQEBAwEBAQcDAQEBgVEGAQEBCwGCaU8hOYwQX5Ytji4UgWYNG4RRAoNDNA0NAQMBAQIBAQJtHAyFOwZ5EFEhNgYOBYMhAYFpAxWpBId6DYIZCQGHSIYCP4EQAYVogWEMFoYAAp8eLgcCgRGBBwSEV4Z7gyALGIlPhx+OJYlMgUM4gVUzGiSDOwmCHheBc4FQilo+AzABjUMBAQ X-IronPort-AV: E=Sophos;i="5.54,483,1534802400"; d="scan'208";a="51714119" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP12EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaS26.fraunhofer.de with ESMTP/TLS/AES256-SHA; 09 Nov 2018 14:00:06 +0100 Received: from muc-nb-035.aisec.fraunhofer.de (10.80.233.51) by FGDEMUCIMP12EXC.ads.fraunhofer.de (10.80.232.43) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 9 Nov 2018 14:00:06 +0100 From: Lukas Auer To: Date: Fri, 9 Nov 2018 13:59:04 +0100 Message-ID: <20181109125923.7034-10-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181109125923.7034-1-lukas.auer@aisec.fraunhofer.de> References: <20181109125923.7034-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24212.007 X-TM-AS-Result: No--1.995600-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Greentime Hu Subject: [U-Boot] [PATCH v3 09/28] riscv: make use of the barrier functions from Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Replace the barrier functions in arch/riscv/include/asm/io.h with those defined in barrier.h, which is imported from Linux. This version is modified to remove the include statement of asm-generic/barrier.h, which is not available in U-Boot or required. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v3: None Changes in v2: None arch/riscv/include/asm/barrier.h | 67 ++++++++++++++++++++++++++++++++ arch/riscv/include/asm/io.h | 11 ++---- 2 files changed, 71 insertions(+), 7 deletions(-) create mode 100644 arch/riscv/include/asm/barrier.h diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h new file mode 100644 index 0000000000..a3f60a8458 --- /dev/null +++ b/arch/riscv/include/asm/barrier.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2013 Regents of the University of California + * Copyright (C) 2017 SiFive + * + * Taken from Linux arch/riscv/include/asm/barrier.h, which is based on + * arch/arm/include/asm/barrier.h + */ + +#ifndef _ASM_RISCV_BARRIER_H +#define _ASM_RISCV_BARRIER_H + +#ifndef __ASSEMBLY__ + +#define nop() __asm__ __volatile__ ("nop") + +#define RISCV_FENCE(p, s) \ + __asm__ __volatile__ ("fence " #p "," #s : : : "memory") + +/* These barriers need to enforce ordering on both devices or memory. */ +#define mb() RISCV_FENCE(iorw,iorw) +#define rmb() RISCV_FENCE(ir,ir) +#define wmb() RISCV_FENCE(ow,ow) + +/* These barriers do not need to enforce ordering on devices, just memory. */ +#define __smp_mb() RISCV_FENCE(rw,rw) +#define __smp_rmb() RISCV_FENCE(r,r) +#define __smp_wmb() RISCV_FENCE(w,w) + +#define __smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(rw,w); \ + WRITE_ONCE(*p, v); \ +} while (0) + +#define __smp_load_acquire(p) \ +({ \ + typeof(*p) ___p1 = READ_ONCE(*p); \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(r,rw); \ + ___p1; \ +}) + +/* + * This is a very specific barrier: it's currently only used in two places in + * the kernel, both in the scheduler. See include/linux/spinlock.h for the two + * orderings it guarantees, but the "critical section is RCsc" guarantee + * mandates a barrier on RISC-V. The sequence looks like: + * + * lr.aq lock + * sc lock <= LOCKED + * smp_mb__after_spinlock() + * // critical section + * lr lock + * sc.rl lock <= UNLOCKED + * + * The AQ/RL pair provides a RCpc critical section, but there's not really any + * way we can take advantage of that here because the ordering is only enforced + * on that one lock. Thus, we're just doing a full fence. + */ +#define smp_mb__after_spinlock() RISCV_FENCE(rw,rw) + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_BARRIER_H */ diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 472814a13e..d01ed5bc9f 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -10,6 +10,7 @@ #ifdef __KERNEL__ #include +#include #include static inline void sync(void) @@ -91,13 +92,9 @@ static inline phys_addr_t virt_to_phys(void *vaddr) #define __raw_readl(a) __arch_getl(a) #define __raw_readq(a) __arch_getq(a) -/* - * TODO: The kernel offers some more advanced versions of barriers, it might - * have some advantages to use them instead of the simple one here. - */ -#define dmb() __asm__ __volatile__ ("" : : : "memory") -#define __iormb() dmb() -#define __iowmb() dmb() +#define dmb() mb() +#define __iormb() rmb() +#define __iowmb() wmb() static inline void writeb(u8 val, volatile void __iomem *addr) {