From patchwork Mon Nov 5 18:02:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajesh Bhagat X-Patchwork-Id: 993320 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="QSp7n90e"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42ph5z2x49z9sDr for ; Tue, 6 Nov 2018 05:29:11 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 21DF2C226FC; Mon, 5 Nov 2018 18:19:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 496F7C226F1; Mon, 5 Nov 2018 18:19:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B19CBC226D1; Mon, 5 Nov 2018 18:02:49 +0000 (UTC) Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-db5eur01on0059.outbound.protection.outlook.com [104.47.2.59]) by lists.denx.de (Postfix) with ESMTPS id 1FFA3C2268D for ; Mon, 5 Nov 2018 18:02:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=t4Rzp0cxDs4iwMUU186XbQ9bmBiao7PfZodRrMOh6Sg=; b=QSp7n90eTRcUm136Pw+R4oVXi5bXkwM9m7L41pXHENf9c9lAaPrxa6ChyPMPeZq2RSXXpy+lu8EHyllzQXScS8nkcvHYci8hqWRuaB18RFbS7Ei6pROYfD6mtY2QTKWo37/QB6p2xMo7GqIsG/xDt0gnpPgePG5Z8d+c4Mk5AKQ= Received: from VI1PR04MB4863.eurprd04.prod.outlook.com (20.177.49.148) by VI1PR04MB3023.eurprd04.prod.outlook.com (10.170.228.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1294.24; Mon, 5 Nov 2018 18:02:44 +0000 Received: from VI1PR04MB4863.eurprd04.prod.outlook.com ([fe80::2927:ca76:cff0:bd50]) by VI1PR04MB4863.eurprd04.prod.outlook.com ([fe80::2927:ca76:cff0:bd50%4]) with mapi id 15.20.1294.028; Mon, 5 Nov 2018 18:02:44 +0000 From: Rajesh Bhagat To: "u-boot@lists.denx.de" Thread-Topic: [PATCH v6 22/27] armv8: ls1043ardb: Add TFABOOT support Thread-Index: AQHUdTHAKSs81veUA0eAYiK4dQXEDw== Date: Mon, 5 Nov 2018 18:02:44 +0000 Message-ID: <20181105181931.7348-23-rajesh.bhagat@nxp.com> References: <20181105181931.7348-1-rajesh.bhagat@nxp.com> In-Reply-To: <20181105181931.7348-1-rajesh.bhagat@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.17.1 x-originating-ip: [14.143.30.134] x-clientproxiedby: OSAPR01CA0003.jpnprd01.prod.outlook.com (2603:1096:603:2a::15) To VI1PR04MB4863.eurprd04.prod.outlook.com (2603:10a6:803:56::20) authentication-results: spf=none (sender IP is ) smtp.mailfrom=rajesh.bhagat@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; VI1PR04MB3023; 6:gLt27ZTONl+DYIIEDWGrg2Z1MFH9+NeyhmyLyzYIwR+clOyqfEfVVRTCIwHRCXGvV+CrHhqL3UFo1cQY4rS0C7ZqeNb8cNnwOwgW2wY/DYxAaGdc2/HrP149UriK1E3tSlhTYDHOpShWN0v+j0llR7IczaDRd5crEZk686JdoVvetYlDK8+91pB0jxIq3VWzabHx+8hNBqZ+pBb1Ou4ZAOJsPNes7ieJsvlRdplMPupx0bLiXIA/D1pdkaVGl4+M7IWPPrLMrjmFNfU4QGixhv7kX8oWtXtOXqVqQ7dij6rnYN0+i4SmGa5HXgKajmKGI8He0tqnpJnzCxub+t5oCXRxu7GB0uuYoai+hD+71KpN5GXm996Bm5zdGOCRFI9gGjWUlBx1d26UR/KSpqmsGSJYToi0I4dRUcvAZYBfOHk5sXUthjV2nQUOQBg/5Tba9rrcXlN12wvQeWiLsX5MNQ==; 5:EC9m6xLri3RaS6SvI6eGHyEPZB8UEaw5zLQyZ5S94yAR9t5J0yzhwxTh/l+l0Bs32SBptXoRZp5d9zOmVYNZHQTVLMe7LQ5o6OYl52SxUjioi3EkdTmXHOGi4SiW8gQ8Z+wYCkn/17HXHrrq5sD/Dl90zyhmetkIATCviZ/Pqmc=; 7:zQVPLFDpb/96Wol4S19M2dO4NiHT+uNc87/fIkn4hPvP0V12Po5wnQ5EbPYwRV/aKrt0a4Kvp/IngQEH5QNiMiawlp7Z8iIxTXIWzV4NIXbWwHJSnGjC4G27CJC3i6346+xoU3h+fTg7q0thzIVdPA== x-ms-office365-filtering-correlation-id: f631c223-fd2b-4e66-ddd4-08d64348e2d9 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:VI1PR04MB3023; x-ms-traffictypediagnostic: VI1PR04MB3023: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(185117386973197); x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(10201501046)(3002001)(3231382)(944501410)(52105095)(6055026)(148016)(149066)(150057)(6041310)(20161123558120)(20161123564045)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095); SRVR:VI1PR04MB3023; BCL:0; PCL:0; RULEID:; SRVR:VI1PR04MB3023; x-forefront-prvs: 08476BC6EF x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(396003)(136003)(346002)(376002)(39860400002)(366004)(189003)(199004)(4326008)(97736004)(6116002)(1076002)(78486014)(7736002)(305945005)(14444005)(256004)(446003)(50226002)(3846002)(2501003)(5660300001)(6916009)(476003)(486006)(6512007)(81166006)(8676002)(81156014)(36756003)(44832011)(5640700003)(6486002)(4744004)(26005)(6436002)(2616005)(71190400001)(71200400001)(8936002)(66066001)(53936002)(54906003)(6506007)(105586002)(25786009)(386003)(316002)(106356001)(55236004)(102836004)(11346002)(186003)(68736007)(2900100001)(2906002)(478600001)(99286004)(52116002)(76176011)(575784001)(2351001)(14454004)(86362001); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB3023; H:VI1PR04MB4863.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: LkwA+g9E1XMcX2gU5zdd0hys60shBltdn1E/DT2jnac0CTu/EA0XQWkyEQN9CJHD7LdxYCdTh4E8eDIWp8//8C1OfOFUyCJflJzbq9FuN1UVKy70y8AkkIlLL6GHmMbgJz9Zgtfv0WgOBpmXJPpoNE9GE+TYf/jipaUsIyWUvbcd1MFNMYE8vYDULgKnRU7k/D3BLQSdaIPqgDL6V6+GxzVgibZBs9AYj1AebeJ6V/qwWfjYZEwCGImzTK5dGwEb/Ws5S2lEfbeofAHQXyH5rZ+l6qOTqJlYA3LgdahPSA0iw7UXRT5PKyfMpso6KNZOib8ZvzgMpa/0xbtA7SYAxdMmKN+o3PMlqhFy2gyQKQk= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f631c223-fd2b-4e66-ddd4-08d64348e2d9 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Nov 2018 18:02:44.6372 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB3023 Cc: Pankit Garg , Vinitha V Pillai Subject: [U-Boot] [PATCH v6 22/27] armv8: ls1043ardb: Add TFABOOT support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" TFABOOT support includes: - ls1043ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN and QE address changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: Pankit Garg Signed-off-by: Vinitha V Pillai Signed-off-by: Rajesh Bhagat --- Change in v6: - Rebased to master Change in v5: None Change in v4: None Change in v3: - Added ls1046ardb_tfa_SECURE_BOOT_defconfig Change in v2: - Merged ls1046ardb TFA boot support patches - Removed extra CONFIG_TFABOOT flag usage board/freescale/ls1043ardb/MAINTAINERS | 2 + board/freescale/ls1043ardb/ddr.c | 14 +++ board/freescale/ls1043ardb/ls1043ardb.c | 110 +++++++++++++++++++ configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 55 ++++++++++ configs/ls1043ardb_tfa_defconfig | 52 +++++++++ include/configs/ls1043a_common.h | 27 ++++- include/configs/ls1043ardb.h | 29 +++++ 7 files changed, 288 insertions(+), 1 deletion(-) create mode 100644 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1043ardb_tfa_defconfig diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS index 88fe42e1e8..3f64a6fc02 100644 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -1,5 +1,6 @@ LS1043A BOARD M: Mingkai Hu +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1043ardb/ F: board/freescale/ls1043ardb/ls1043ardb.c @@ -7,6 +8,7 @@ F: include/configs/ls1043ardb.h F: configs/ls1043ardb_defconfig F: configs/ls1043ardb_nand_defconfig F: configs/ls1043ardb_sdcard_defconfig +F: configs/ls1043ardb_tfa_defconfig LS1043A_SECURE_BOOT BOARD M: Ruchika Gupta diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 7bc0f568ff..784e482f32 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -205,6 +205,19 @@ phys_size_t fixed_sdram(void) } #endif +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) +#ifdef CONFIG_SYS_DDR_RAW_TIMING + gd->ram_size = fsl_ddr_sdram_size(); +#else + gd->ram_size = 0x80000000; +#endif + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -236,3 +249,4 @@ int fsl_initdram(void) return 0; } +#endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index f31f0ec515..fbd9a2691b 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -27,6 +27,104 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor", + CONFIG_SYS_NOR_CSPR, + CONFIG_SYS_NOR_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "cpld", + CONFIG_SYS_CPLD_CSPR, + CONFIG_SYS_CPLD_CSPR_EXT, + CONFIG_SYS_CPLD_AMASK, + CONFIG_SYS_CPLD_CSOR, + { + CONFIG_SYS_CPLD_FTIM0, + CONFIG_SYS_CPLD_FTIM1, + CONFIG_SYS_CPLD_FTIM2, + CONFIG_SYS_CPLD_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor", + CONFIG_SYS_NOR_CSPR, + CONFIG_SYS_NOR_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "cpld", + CONFIG_SYS_CPLD_CSPR, + CONFIG_SYS_CPLD_CSPR_EXT, + CONFIG_SYS_CPLD_AMASK, + CONFIG_SYS_CPLD_CSOR, + { + CONFIG_SYS_CPLD_FTIM0, + CONFIG_SYS_CPLD_FTIM1, + CONFIG_SYS_CPLD_FTIM2, + CONFIG_SYS_CPLD_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +#endif int board_early_init_f(void) { fsl_lsch2_early_init_f(); @@ -38,6 +136,9 @@ int board_early_init_f(void) int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; #ifndef CONFIG_SD_BOOT u8 cfg_rcw_src1, cfg_rcw_src2; @@ -47,6 +148,12 @@ int checkboard(void) printf("Board: LS1043ARDB, boot from "); +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -64,6 +171,9 @@ int checkboard(void) printf("Invalid setting of SW4\n"); #endif +#ifdef CONFIG_TFABOOT + } +#endif printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..0ad9db7736 --- /dev/null +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SECURE_BOOT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_TFABOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_DM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_CAAM=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig new file mode 100644 index 0000000000..662a966ebe --- /dev/null +++ b/configs/ls1043ardb_tfa_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 4279d53549..27350dfa00 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -33,7 +33,11 @@ #include /* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif #define CONFIG_SKIP_LOWLEVEL_INIT @@ -119,7 +123,8 @@ /* IFC */ #ifndef SPL_NO_IFC -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) #define CONFIG_FSL_IFC /* * CONFIG_SYS_FLASH_BASE has the final address (core view) @@ -182,6 +187,16 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 +#define CONFIG_SYS_QE_FW_ADDR 0x940000 + +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 + +#else #ifdef CONFIG_NAND_BOOT /* Store Fman ucode at offeset 0x900000(72 blocks). */ #define CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -208,6 +223,7 @@ #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 #endif +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif @@ -300,6 +316,14 @@ #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" @@ -311,6 +335,7 @@ "env exists secureboot && esbc_halt;" #endif #endif +#endif /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 54e6eef417..a0d39878b8 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -162,6 +162,25 @@ #define CONFIG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -199,6 +218,7 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif +#endif #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR @@ -227,6 +247,14 @@ #define CONFIG_ENV_OVERWRITE #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #if defined(CONFIG_NAND_BOOT) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -239,6 +267,7 @@ #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif /* FMan */ #ifndef SPL_NO_FMAN