From patchwork Fri Nov 2 14:21:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 992330 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42mkpq3Wr7zB4Wc for ; Sat, 3 Nov 2018 01:24:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DE696C2253E; Fri, 2 Nov 2018 14:24:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5C018C2250F; Fri, 2 Nov 2018 14:21:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F11C6C224CD; Fri, 2 Nov 2018 14:21:38 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lists.denx.de (Postfix) with ESMTPS id 96238C224CD for ; Fri, 2 Nov 2018 14:21:33 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id wA2ELVq6124111; Fri, 2 Nov 2018 09:21:31 -0500 Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wA2ELVJu005697 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 Nov 2018 09:21:31 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 2 Nov 2018 09:21:31 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 2 Nov 2018 09:21:31 -0500 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wA2ELNGe026724; Fri, 2 Nov 2018 09:21:29 -0500 From: Lokesh Vutla To: Tom Rini , Date: Fri, 2 Nov 2018 19:51:03 +0530 Message-ID: <20181102142111.19766-3-lokeshvutla@ti.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181102142111.19766-1-lokeshvutla@ti.com> References: <20181102142111.19766-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH v4 02/10] armv7R: K3: am654: Enable MPU regions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable MPU regions for AM654 evm: - Region0: 0x00000000 - 0xFFFFFFFF: Device memory, not executable - Region1: 0x41c00000 - 0x42400000: Normal, executable, WB, Write alloc - Region2: 0x80000000 - 0xFFFFFFFF: Normal, executable, WB, Write alloc - region3-15: Disabled With this dcache can be enabled either in SPL or U-Boot. Reviewed-by: Tom Rini Signed-off-by: Lokesh Vutla --- arch/arm/mach-k3/Makefile | 1 + arch/arm/mach-k3/am6_init.c | 5 ++++ arch/arm/mach-k3/common.h | 11 +++++++++ arch/arm/mach-k3/r5_mpu.c | 47 +++++++++++++++++++++++++++++++++++++ 4 files changed, 64 insertions(+) create mode 100644 arch/arm/mach-k3/common.h create mode 100644 arch/arm/mach-k3/r5_mpu.c diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index e9b7ee5210..619733fb87 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o obj-$(CONFIG_ARM64) += arm64-mmu.o +obj-$(CONFIG_CPU_V7R) += r5_mpu.o diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 68f0b8c011..fef0107505 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -10,6 +10,7 @@ #include #include #include +#include "common.h" #ifdef CONFIG_SPL_BUILD static void mmr_unlock(u32 base, u32 partition) @@ -65,6 +66,10 @@ void board_init_f(ulong dummy) /* Make all control module registers accessible */ ctrl_mmr_unlock(); +#ifdef CONFIG_CPU_V7R + setup_k3_mpu_regions(); +#endif + /* Init DM early in-order to invoke system controller */ spl_early_init(); diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h new file mode 100644 index 0000000000..ac7e80d9af --- /dev/null +++ b/arch/arm/mach-k3/common.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: Architecture common definitions + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#include + +void setup_k3_mpu_regions(void); diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c new file mode 100644 index 0000000000..ee076ed877 --- /dev/null +++ b/arch/arm/mach-k3/r5_mpu.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * K3: R5 MPU region definitions + * + * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#include +#include +#include +#include "common.h" + +struct mpu_region_config k3_mpu_regions[16] = { + /* + * Make all 4GB as Device Memory and not executable. We are overriding + * it with next region for any requirement. + */ + {0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, SHARED_WRITE_BUFFERED, + REGION_4GB}, + + /* SPL code area marking it as WB and Write allocate. */ + {CONFIG_SPL_TEXT_BASE, REGION_1, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_8MB}, + + /* U-Boot's code area marking it as WB and Write allocate */ + {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_2GB}, + {0x0, 3, 0x0, 0x0, 0x0, 0x0}, + {0x0, 4, 0x0, 0x0, 0x0, 0x0}, + {0x0, 5, 0x0, 0x0, 0x0, 0x0}, + {0x0, 6, 0x0, 0x0, 0x0, 0x0}, + {0x0, 7, 0x0, 0x0, 0x0, 0x0}, + {0x0, 8, 0x0, 0x0, 0x0, 0x0}, + {0x0, 9, 0x0, 0x0, 0x0, 0x0}, + {0x0, 10, 0x0, 0x0, 0x0, 0x0}, + {0x0, 11, 0x0, 0x0, 0x0, 0x0}, + {0x0, 12, 0x0, 0x0, 0x0, 0x0}, + {0x0, 13, 0x0, 0x0, 0x0, 0x0}, + {0x0, 14, 0x0, 0x0, 0x0, 0x0}, + {0x0, 15, 0x0, 0x0, 0x0, 0x0}, +}; + +void setup_k3_mpu_regions(void) +{ + setup_mpu_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions)); +}