From patchwork Thu Oct 25 08:00:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 988945 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="ebuF4jkR"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42gfpr6fvfz9sB5 for ; Thu, 25 Oct 2018 19:06:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DF1D4C21F1B; Thu, 25 Oct 2018 08:05:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 95709C21FAE; Thu, 25 Oct 2018 08:01:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 09560C21F77; Thu, 25 Oct 2018 08:01:30 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id 21CD0C21F2B for ; Thu, 25 Oct 2018 08:01:24 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9P81MU0084728; Thu, 25 Oct 2018 03:01:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1540454482; bh=cdLM3X7v7EVLRI+PDwFS2ZqmItAjx8omjQlIEWINcUs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ebuF4jkR1GhDvpcytlusbmwIZ+m8mBjQHBP1woeztBWMxyF3AMYGFLO5RxTbU0Yad GnFjLSeMs+mhdUYR0enZbGAILPaSBWHGJgV0DFTFAAS3UPBTSfJ6seF6Phtmj/NrQb 3Uwh/tSA16EGrz5w977YZ1rlknk6JhYPo93n0TtU= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9P81Mbx020737; Thu, 25 Oct 2018 03:01:22 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 25 Oct 2018 03:01:21 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 25 Oct 2018 03:01:21 -0500 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9P819m9015380; Thu, 25 Oct 2018 03:01:20 -0500 From: Lokesh Vutla To: Tom Rini , Date: Thu, 25 Oct 2018 13:30:54 +0530 Message-ID: <20181025080100.30176-5-lokeshvutla@ti.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181025080100.30176-1-lokeshvutla@ti.com> References: <20181025080100.30176-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH v3 04/10] armv7R: K3: am654: Add support to start ATF from R5 SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Considering the boot time requirements, Cortex-A core should be able to start immediately after SPL on R5. Add support for the same. Reviewed-by: Tom Rini Signed-off-by: Lokesh Vutla --- arch/arm/mach-k3/Kconfig | 7 ++++++ arch/arm/mach-k3/Makefile | 1 + arch/arm/mach-k3/common.c | 52 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 arch/arm/mach-k3/common.c diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 9f5e8e5ee4..e677a2e01b 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -58,5 +58,12 @@ config SYS_K3_BOOT_CORE_ID int default 16 +config SYS_K3_SPL_ATF + bool "Start Cortex-A from SPL" + depends on SPL && CPU_V7R + help + Enabling this will try to start Cortex-A (typically with ATF) + after SPL from R5. + source "board/ti/am65x/Kconfig" endif diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 619733fb87..406dda3b02 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o +obj-y += common.o diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c new file mode 100644 index 0000000000..cc89d4a296 --- /dev/null +++ b/arch/arm/mach-k3/common.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * K3: Common Architecture initialization + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#include +#include +#include "common.h" +#include +#include + +#ifdef CONFIG_SYS_K3_SPL_ATF +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + int ret; + + /* + * It is assumed that remoteproc device 1 is the corresponding + * cortex A core which runs ATF. Make sure DT reflects the same. + */ + ret = rproc_dev_init(1); + if (ret) { + printf("%s: ATF failed to Initialize on rproc: ret= %d\n", + __func__, ret); + hang(); + } + + ret = rproc_load(1, spl_image->entry_point, 0x200); + if (ret) { + printf("%s: ATF failed to load on rproc: ret= %d\n", + __func__, ret); + hang(); + } + + /* Add an extra newline to differentiate the ATF logs from SPL*/ + printf("Starting ATF on ARM64 core...\n\n"); + + ret = rproc_start(1); + if (ret) { + printf("%s: ATF failed to start on rproc: ret= %d\n", + __func__, ret); + hang(); + } + + debug("ATF started. Wait indefiniely\n"); + while (1) + asm volatile("wfe"); +} +#endif