From patchwork Thu Oct 18 12:28:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anatolij Gustschin X-Patchwork-Id: 985857 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42bTJR21vcz9s89 for ; Thu, 18 Oct 2018 23:44:23 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CD216C21DD4; Thu, 18 Oct 2018 12:41:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A8406C21F3B; Thu, 18 Oct 2018 12:29:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5FC32C21F21; Thu, 18 Oct 2018 12:29:34 +0000 (UTC) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by lists.denx.de (Postfix) with ESMTPS id 8DDBFC21D56 for ; Thu, 18 Oct 2018 12:29:19 +0000 (UTC) Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 42bSz32rMzz1qxDQ; Thu, 18 Oct 2018 14:29:19 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 42bSz32hYgz1qqkH; Thu, 18 Oct 2018 14:29:19 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id r9et2TsdIeMr; Thu, 18 Oct 2018 14:29:18 +0200 (CEST) X-Auth-Info: wX0U9OYlb1uEqivJKjtJZ3g7KamTG4xu6Li4OUs67fI= Received: from crub.agik.hopto.org (p508DEB69.dip0.t-ipconnect.de [80.141.235.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 18 Oct 2018 14:29:18 +0200 (CEST) From: Anatolij Gustschin To: u-boot@lists.denx.de, peng.fan@nxp.com, sbabic@denx.de Date: Thu, 18 Oct 2018 14:28:31 +0200 Message-Id: <20181018122837.31582-29-agust@denx.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181018122837.31582-1-agust@denx.de> References: <20181018122837.31582-1-agust@denx.de> Subject: [U-Boot] [PATCH v6 28/34] serial_lpuart: Update lpuart driver to support i.MX8 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Peng Fan Add i.MX8 compatible string and cpu type support to lpuart driver, to use little endian 32 bits configurations. Also, according to RM, the Receive FIFO Enable (RXFE) field in LPUART FIFO register is bit 3, so this definition should change to 0x08 (not 0x40) for i.MX8, otherwise the Receive FIFO is not disabled. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- drivers/serial/serial_lpuart.c | 15 ++++++++++++--- include/fsl_lpuart.h | 2 +- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 1212b72676..c14a8105c9 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -41,7 +41,11 @@ #define CTRL_RE (1 << 18) #define FIFO_TXFE 0x80 +#ifdef CONFIG_ARCH_IMX8 +#define FIFO_RXFE 0x08 +#else #define FIFO_RXFE 0x40 +#endif #define WATER_TXWATER_OFF 1 #define WATER_RXWATER_OFF 16 @@ -54,7 +58,8 @@ DECLARE_GLOBAL_DATA_PTR; enum lpuart_devtype { DEV_VF610 = 1, DEV_LS1021A, - DEV_MX7ULP + DEV_MX7ULP, + DEV_IMX8 }; struct lpuart_serial_platdata { @@ -325,7 +330,7 @@ static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) lpuart_write32(plat->flags, &base->match, 0); - if (plat->devtype == DEV_MX7ULP) { + if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) { _lpuart32_serial_setbrg_7ulp(plat, gd->baudrate); } else { /* provide data bits, parity, stop bit, etc */ @@ -342,7 +347,7 @@ static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) struct lpuart_serial_platdata *plat = dev->platdata; if (is_lpuart32(dev)) { - if (plat->devtype == DEV_MX7ULP) + if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) _lpuart32_serial_setbrg_7ulp(plat, baudrate); else _lpuart32_serial_setbrg(plat, baudrate); @@ -427,6 +432,8 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) plat->devtype = DEV_MX7ULP; else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) plat->devtype = DEV_VF610; + else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) + plat->devtype = DEV_IMX8; return 0; } @@ -444,6 +451,8 @@ static const struct udevice_id lpuart_serial_ids[] = { { .compatible = "fsl,imx7ulp-lpuart", .data = LPUART_FLAG_REGMAP_32BIT_REG }, { .compatible = "fsl,vf610-lpuart"}, + { .compatible = "fsl,imx8qm-lpuart", + .data = LPUART_FLAG_REGMAP_32BIT_REG }, { } }; diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h index 02ebfefc74..fc517d4b7f 100644 --- a/include/fsl_lpuart.h +++ b/include/fsl_lpuart.h @@ -4,7 +4,7 @@ * */ -#ifdef CONFIG_ARCH_MX7ULP +#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) struct lpuart_fsl_reg32 { u32 verid; u32 param;