From patchwork Tue Oct 16 09:22:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 984635 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42Z99x0X1Yz9s8r for ; Tue, 16 Oct 2018 20:34:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CA9ABC21C50; Tue, 16 Oct 2018 09:28:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 09F44C21E15; Tue, 16 Oct 2018 09:25:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 237BEC21E30; Tue, 16 Oct 2018 09:25:06 +0000 (UTC) Received: from 9.mo6.mail-out.ovh.net (9.mo6.mail-out.ovh.net [87.98.171.146]) by lists.denx.de (Postfix) with ESMTPS id 0750FC21E3E for ; Tue, 16 Oct 2018 09:24:03 +0000 (UTC) Received: from player731.ha.ovh.net (unknown [10.109.146.76]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 6558E189198 for ; Tue, 16 Oct 2018 11:24:01 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 3E11A4200B9; Tue, 16 Oct 2018 11:23:54 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: u-boot@lists.denx.de, Joe Hershberger Date: Tue, 16 Oct 2018 11:22:46 +0200 Message-Id: <20181016092252.11664-8-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016092252.11664-1-clg@kaod.org> References: <20181016092252.11664-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 12551813640467155737 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrfedtgdduhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Cc: Maxim Sloyko Subject: [U-Boot] [PATCH v4 07/13] net: ftgmac100: handle timeouts when transmitting X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley --- Changes since v3 : - introduced a ftgmac100_wait_for_txdone() function similar to the wait_for_bit_*() macros. drivers/net/ftgmac100.c | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index bf8600814690..9adfe109ebc2 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -28,6 +29,9 @@ /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ #define PKTBUFSTX 4 /* must be power of 2 */ +/* Timeout for transmit */ +#define FTGMAC100_TX_TIMEOUT_MS 1000 + /* Timeout for a mdio read/write operation */ #define FTGMAC100_MDIO_TIMEOUT_USEC 10000 @@ -401,6 +405,41 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) return rxlen; } +/* + * The wait_for_bit_*() macros require a register value. This define a + * similar routine which loops on the in-memory transmit descriptor to + * wait for the MAC to clear the DMA_OWN bit. + */ +static int ftgmac100_wait_for_txdone(struct ftgmac100_txdes *txdes, + const unsigned int timeout_ms, + const bool breakable) +{ + ulong des_start = (ulong)txdes; + ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN); + ulong start = get_timer(0); + + while (1) { + invalidate_dcache_range(des_start, des_end); + + if (!(txdes->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN)) + return 0; + + if (get_timer(start) > timeout_ms) + break; + + if (breakable && ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + + udelay(1); + WATCHDOG_RESET(); + } + + dev_err(dev, "transmit timeout\n"); + return -ETIMEDOUT; +} + /* * Send a data block via Ethernet */ @@ -414,6 +453,7 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); ulong data_start; ulong data_end; + int rc; invalidate_dcache_range(des_start, des_end); @@ -446,6 +486,10 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) /* Start transmit */ writel(1, &ftgmac100->txpd); + rc = ftgmac100_wait_for_txdone(curr_des, FTGMAC100_TX_TIMEOUT_MS, true); + if (rc) + return rc; + debug("%s(): packet sent\n", __func__); /* Move to next descriptor */