From patchwork Mon Oct 15 07:24:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Six X-Patchwork-Id: 983934 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gdsys.cc Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42YVYq428Vz9sBj for ; Mon, 15 Oct 2018 18:34:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0C84DC21DB5; Mon, 15 Oct 2018 07:28:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L3, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A89AFC21E62; Mon, 15 Oct 2018 07:24:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 102FEC21BE5; Mon, 15 Oct 2018 07:24:45 +0000 (UTC) Received: from smtprelay06.ispgateway.de (smtprelay06.ispgateway.de [80.67.31.95]) by lists.denx.de (Postfix) with ESMTPS id B5C92C21BE5 for ; Mon, 15 Oct 2018 07:24:45 +0000 (UTC) Received: from [87.191.40.34] (helo=bob3.testumgebung.local) by smtprelay06.ispgateway.de with esmtpa (Exim 4.90_1) (envelope-from ) id 1gBxF5-0004ba-Kp; Mon, 15 Oct 2018 09:24:43 +0200 From: Mario Six To: U-Boot Mailing List , Anatolij Gustschin , Daniel Schwierzeck , Simon Glass , Bin Meng Date: Mon, 15 Oct 2018 09:24:15 +0200 Message-Id: <20181015072418.308-13-mario.six@gdsys.cc> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181015072418.308-1-mario.six@gdsys.cc> References: <20181015072418.308-1-mario.six@gdsys.cc> X-Df-Sender: bWFyaW8uc2l4QGdkc3lzLmNj Subject: [U-Boot] [PATCH v11 13/16] regmap: Add overview documentation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add some overview documentation that explains the purpose and some of the features and limitations of the regmap interface. Reviewed-by: Bin Meng Signed-off-by: Mario Six Reviewed-by: Bin Meng Signed-off-by: Mario Six --- v10 -> v11: No changes v9 -> v10: No changes v8 -> v9: * Amended for inclusion of endianness setting via DT v7 -> v8: New in v8 --- include/regmap.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) -- 2.18.1 diff --git a/include/regmap.h b/include/regmap.h index 98860c2732..b2b733fda6 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -7,6 +7,33 @@ #ifndef __REGMAP_H #define __REGMAP_H +/** + * DOC: Overview + * + * Regmaps are an abstraction mechanism that allows device drivers to access + * register maps irrespective of the underlying bus architecture. This entails + * that for devices that support multiple busses (e.g. I2C and SPI for a GPIO + * expander chip) only one driver has to be written. This driver will + * instantiate a regmap with a backend depending on the bus the device is + * attached to, and use the regmap API to access the register map through that + * bus transparently. + * + * Read and write functions are supplied, which can read/write data of + * arbitrary length from/to the regmap. + * + * The endianness of regmap accesses is selectable for each map through device + * tree settings via the boolean "little-endian", "big-endian", and + * "native-endian" properties. + * + * Furthermore, the register map described by a regmap can be split into + * multiple disjoint areas called ranges. In this way, register maps with + * "holes", i.e. areas of addressable memory that are not part of the register + * map, can be accessed in a concise manner. + * + * Currently, only a bare "mem" backend for regmaps is supported, which + * accesses the register map as regular IO-mapped memory. + */ + /** * enum regmap_size_t - Access sizes for regmap reads and writes *