diff mbox series

[U-Boot,v4,06/27] armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3

Message ID 20181012144454.3707-7-rajesh.bhagat@nxp.com
State Superseded
Delegated to: York Sun
Headers show
Series TF-A Boot support for NXP Chassis 2 platforms | expand

Commit Message

Rajesh Bhagat Oct. 12, 2018, 2:44 p.m. UTC 
From: Pankit Garg <pankit.garg@nxp.com>

Change tlb base address from OCRAM to DDR when exception level is
less than 3.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index bae50f68d8..6304825180 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -371,7 +371,10 @@  static inline void early_mmu_setup(void)
 	unsigned int el = current_el();
 
 	/* global data is already setup, no allocation yet */
-	gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+	if (el == 3)
+		gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+	else
+		gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 	gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 	gd->arch.tlb_size = EARLY_PGTABLE_SIZE;