From patchwork Thu Oct 4 11:39:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 978751 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42QrWt05hFz9s4s for ; Thu, 4 Oct 2018 21:39:21 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id AA623C21C29; Thu, 4 Oct 2018 11:39:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BE639C2201E; Thu, 4 Oct 2018 11:39:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B9840C2201E; Thu, 4 Oct 2018 11:39:11 +0000 (UTC) Received: from mx1.mailbox.org (mx1.mailbox.org [80.241.60.212]) by lists.denx.de (Postfix) with ESMTPS id 5995FC21C29 for ; Thu, 4 Oct 2018 11:39:11 +0000 (UTC) Received: from smtp1.mailbox.org (unknown [IPv6:2001:67c:2050:105:465:1:1:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.mailbox.org (Postfix) with ESMTPS id 3EEC849965; Thu, 4 Oct 2018 13:39:11 +0200 (CEST) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp1.mailbox.org ([80.241.60.240]) by spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de [80.241.56.116]) (amavisd-new, port 10030) with ESMTP id Q0SbkNCBZA-J; Thu, 4 Oct 2018 13:39:10 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Thu, 4 Oct 2018 13:39:07 +0200 Message-Id: <20181004113908.5004-3-sr@denx.de> In-Reply-To: <20181004113908.5004-1-sr@denx.de> References: <20181004113908.5004-1-sr@denx.de> MIME-Version: 1.0 Subject: [U-Boot] [PATCH] wdt: Add MT7621 watchdog driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds watchdog support for the Mediatek MT7621 SoC. The driver is loosly based on the Linux kernel version. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck Reviewed-by: Daniel Schwierzeck --- drivers/watchdog/Kconfig | 7 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/mt7621_wdt.c | 102 ++++++++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 drivers/watchdog/mt7621_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index d545b3e000..e33c28b24d 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -111,4 +111,11 @@ config XILINX_TB_WATCHDOG Select this to enable Xilinx Axi watchdog timer, which can be found on some Xilinx Microblaze Platforms. +config WDT_MT7621 + bool "MediaTek MT7621 watchdog timer support" + depends on WDT && ARCH_MT7620 + help + Select this to enable Ralink / Mediatek watchdog timer, + which can be found on some MediaTek chips. + endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 08406caa0f..d8a593d602 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -23,3 +23,4 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o +obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c new file mode 100644 index 0000000000..38866141e4 --- /dev/null +++ b/drivers/watchdog/mt7621_wdt.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ralink / Mediatek RT288x/RT3xxx/MT76xx built-in hardware watchdog timer + * + * Copyright (C) 2018 Stefan Roese + * + * Based on the Linux driver version which is: + * Copyright (C) 2011 Gabor Juhos + * Copyright (C) 2013 John Crispin + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct mt762x_wdt { + void __iomem *regs; +}; + +#define TIMER_REG_TMRSTAT 0x00 +#define TIMER_REG_TMR1CTL 0x20 +#define TIMER_REG_TMR1LOAD 0x24 + +#define TMR1CTL_ENABLE BIT(7) +#define TMR1CTL_RESTART BIT(9) +#define TMR1CTL_PRESCALE_SHIFT 16 + +static int mt762x_wdt_ping(struct mt762x_wdt *priv) +{ + writel(TMR1CTL_RESTART, priv->regs + TIMER_REG_TMRSTAT); + + return 0; +} + +static int mt762x_wdt_start(struct udevice *dev, u64 ms, ulong flags) +{ + struct mt762x_wdt *priv = dev_get_priv(dev); + + /* set the prescaler to 1ms == 1000us */ + writel(1000 << TMR1CTL_PRESCALE_SHIFT, priv->regs + TIMER_REG_TMR1CTL); + writel(ms, priv->regs + TIMER_REG_TMR1LOAD); + + setbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE); + + return 0; +} + +static int mt762x_wdt_stop(struct udevice *dev) +{ + struct mt762x_wdt *priv = dev_get_priv(dev); + + mt762x_wdt_ping(priv); + + clrbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE); + + return 0; +} + +static int mt762x_wdt_reset(struct udevice *dev) +{ + struct mt762x_wdt *priv = dev_get_priv(dev); + + mt762x_wdt_ping(priv); + + return 0; +} + +static int mt762x_wdt_probe(struct udevice *dev) +{ + struct mt762x_wdt *priv = dev_get_priv(dev); + + priv->regs = dev_remap_addr(dev); + if (!priv->regs) + return -EINVAL; + + mt762x_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops mt762x_wdt_ops = { + .start = mt762x_wdt_start, + .reset = mt762x_wdt_reset, + .stop = mt762x_wdt_stop, +}; + +static const struct udevice_id mt762x_wdt_ids[] = { + { .compatible = "mediatek,mt7621-wdt" }, + {} +}; + +U_BOOT_DRIVER(mt762x_wdt) = { + .name = "mt762x_wdt", + .id = UCLASS_WDT, + .of_match = mt762x_wdt_ids, + .probe = mt762x_wdt_probe, + .priv_auto_alloc_size = sizeof(struct mt762x_wdt), + .ops = &mt762x_wdt_ops, +};