From patchwork Mon Oct 1 18:22:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 977409 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42PBGh5512z9s55 for ; Tue, 2 Oct 2018 04:52:12 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 65C58C21F7E; Mon, 1 Oct 2018 18:42:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D5B87C22080; Mon, 1 Oct 2018 18:25:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AEC81C22076; Mon, 1 Oct 2018 18:24:11 +0000 (UTC) Received: from mail-it1-f201.google.com (mail-it1-f201.google.com [209.85.166.201]) by lists.denx.de (Postfix) with ESMTPS id 4E943C22031 for ; Mon, 1 Oct 2018 18:24:02 +0000 (UTC) Received: by mail-it1-f201.google.com with SMTP id u2-v6so5207393ith.1 for ; Mon, 01 Oct 2018 11:24:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=1QWqIpR2Rp8ql1KxfRqbz9CoyZ+Eov+4+oE9BUcRV0s=; b=G0W9abMmvQcr+R86Gj/OI6R4h31UKGjRMUyJIerTlyQUcyJAAOOiptnltVSHIdAAxm W/suUrhqQPBrECAqwdALNBDrDIbH2WZKzcz0zNfOFYZd9Wn+GQ6xmE481k57q3SEprwQ WECNPRLxyUQ2utAQnmnrVQYkpvejGNhrBxihOEwFy/fq6mwTCuI9JTASiBrnORy7KzJI aqdSU7JNmX00ad6vQN813Xno6KHKFjUU5mI8QzOlzjbb3ymYSxoDqDrgXGvaFD6wXfT8 cPF5tirJFja8SVDG2dGbtj/jwUX+Zk76LflQQdZ+Up+RyYOQUoz9rLNvTZh44GFV1pp5 tkVQ== X-Gm-Message-State: ABuFfohF+haGvinko8WDYoZfLr6kPojbBMaqlne+v2gouEwh2CWf0sMx 5/cazGtPB1aTyYYyCay0WoJUS6A= X-Google-Smtp-Source: ACcGV61dxtBh/2lQvJCLSW2SkK6oz9DC+ZgAANJzGArZ9k8R1B5wtik82fuqr2EDuOQFirfF7DL5KfE= X-Received: by 2002:a24:93c5:: with SMTP id y188-v6mr12257797itd.1.1538418241355; Mon, 01 Oct 2018 11:24:01 -0700 (PDT) Date: Mon, 1 Oct 2018 12:22:37 -0600 In-Reply-To: <20181001182249.129565-1-sjg@chromium.org> Message-Id: <20181001182249.129565-34-sjg@chromium.org> Mime-Version: 1.0 References: <20181001182249.129565-1-sjg@chromium.org> X-Mailer: git-send-email 2.19.0.605.g01d371f741-goog From: Simon Glass To: U-Boot Mailing List Subject: [U-Boot] [PATCH 33/45] x86: Update mtrr functions to allow leaving cache alone X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present the mtrr functions disable the cache before making changes and enable it again afterwards. This is fine in U-Boot, but does not work if running in CAR (such as we are in SPL). Update the functions so that the caller can request that caches be left alone. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Bin Meng --- arch/x86/cpu/mtrr.c | 31 +++++++++++++++++++++++-------- arch/x86/include/asm/mtrr.h | 6 ++++-- cmd/x86/mtrr.c | 8 ++++---- 3 files changed, 31 insertions(+), 14 deletions(-) diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 30940065621..0939736164d 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -11,6 +11,11 @@ * System Programming */ +/* + * Note that any console output (e.g. debug()) in this file will likely fail + * since the MTRR registers are sometimes in flux. + */ + #include #include #include @@ -19,27 +24,29 @@ DECLARE_GLOBAL_DATA_PTR; /* Prepare to adjust MTRRs */ -void mtrr_open(struct mtrr_state *state) +void mtrr_open(struct mtrr_state *state, bool do_caches) { if (!gd->arch.has_mtrr) return; - state->enable_cache = dcache_status(); + if (do_caches) { + state->enable_cache = dcache_status(); - if (state->enable_cache) - disable_caches(); + if (state->enable_cache) + disable_caches(); + } state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR); wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN); } /* Clean up after adjusting MTRRs, and enable them */ -void mtrr_close(struct mtrr_state *state) +void mtrr_close(struct mtrr_state *state, bool do_caches) { if (!gd->arch.has_mtrr) return; wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN); - if (state->enable_cache) + if (do_caches && state->enable_cache) enable_caches(); } @@ -50,10 +57,14 @@ int mtrr_commit(bool do_caches) uint64_t mask; int i; + debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr, + gd->arch.mtrr_req_count); if (!gd->arch.has_mtrr) return -ENOSYS; - mtrr_open(&state); + debug("open\n"); + mtrr_open(&state, do_caches); + debug("open done\n"); for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) { mask = ~(req->size - 1); mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; @@ -62,9 +73,12 @@ int mtrr_commit(bool do_caches) } /* Clear the ones that are unused */ + debug("clear\n"); for (; i < MTRR_COUNT; i++) wrmsrl(MTRR_PHYS_MASK_MSR(i), 0); - mtrr_close(&state); + debug("close\n"); + mtrr_close(&state, do_caches); + debug("mtrr done\n"); return 0; } @@ -74,6 +88,7 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size) struct mtrr_request *req; uint64_t mask; + debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count); if (!gd->arch.has_mtrr) return -ENOSYS; diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 05cd7b7f17b..2d897f82ef7 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -77,8 +77,9 @@ struct mtrr_state { * possibly the cache. * * @state: Empty structure to pass in to hold settings + * @do_caches: true to disable caches before opening */ -void mtrr_open(struct mtrr_state *state); +void mtrr_open(struct mtrr_state *state, bool do_caches); /** * mtrr_open() - Clean up after adjusting MTRRs, and enable them @@ -86,8 +87,9 @@ void mtrr_open(struct mtrr_state *state); * This uses the structure containing information returned from mtrr_open(). * * @state: Structure from mtrr_open() + * @state: true to restore cache state to that before mtrr_open() */ -void mtrr_close(struct mtrr_state *state); +void mtrr_close(struct mtrr_state *state, bool do_caches); /** * mtrr_add_request() - Add a new MTRR request diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c index 70f373a72a5..d3fd959235f 100644 --- a/cmd/x86/mtrr.c +++ b/cmd/x86/mtrr.c @@ -73,10 +73,10 @@ static int do_mtrr_set(uint reg, int argc, char * const argv[]) mask |= MTRR_PHYS_MASK_VALID; printf("base=%llx, mask=%llx\n", base, mask); - mtrr_open(&state); + mtrr_open(&state, true); wrmsrl(MTRR_PHYS_BASE_MSR(reg), base); wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask); - mtrr_close(&state); + mtrr_close(&state, true); return 0; } @@ -86,14 +86,14 @@ static int mtrr_set_valid(int reg, bool valid) struct mtrr_state state; uint64_t mask; - mtrr_open(&state); + mtrr_open(&state, true); mask = native_read_msr(MTRR_PHYS_MASK_MSR(reg)); if (valid) mask |= MTRR_PHYS_MASK_VALID; else mask &= ~MTRR_PHYS_MASK_VALID; wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask); - mtrr_close(&state); + mtrr_close(&state, true); return 0; }