From patchwork Fri Sep 28 11:20:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Six X-Patchwork-Id: 976248 X-Patchwork-Delegate: mario.six@gdsys.cc Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gdsys.cc Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42M8Xr6nVLz9s3x for ; Fri, 28 Sep 2018 21:27:24 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 9328CC21F51; Fri, 28 Sep 2018 11:23:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.1 required=5.0 tests=RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,UPPERCASE_50_75 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4DA05C21F78; Fri, 28 Sep 2018 11:21:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C5BBAC21DDC; Fri, 28 Sep 2018 11:21:11 +0000 (UTC) Received: from smtprelay05.ispgateway.de (smtprelay05.ispgateway.de [80.67.31.97]) by lists.denx.de (Postfix) with ESMTPS id F19FDC21DFA for ; Fri, 28 Sep 2018 11:21:10 +0000 (UTC) Received: from [80.151.34.241] (helo=bob3.testumgebung.local) by smtprelay05.ispgateway.de with esmtpa (Exim 4.90_1) (envelope-from ) id 1g5qpY-0000ap-55; Fri, 28 Sep 2018 13:21:08 +0200 From: Mario Six To: U-Boot Mailing List , Wolfgang Denk , Reinhard Arlt , Sinan Akman , York Sun , Heiko Schocher , Paul Gortmaker , Peter Tyser Date: Fri, 28 Sep 2018 13:20:16 +0200 Message-Id: <20180928112038.20984-1-mario.six@gdsys.cc> X-Mailer: git-send-email 2.11.0 X-Df-Sender: bWFyaW8uc2l4QGdkc3lzLmNj Subject: [U-Boot] [PATCH 26/48] mpc8315erdb: Merge BR/OR settings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The mpc8315erdb has the option of either configuring the eLBC (enhanced local system bus) such that * NOR flash is the first memory bank, and NAND flash is the second memory bank, or * NAND flash is the first memory bank, and NOR flash is the second memory bank, by using CONFIG_SYS_NOR_{BR,OR}_PRELIM and CONFIG_SYS_NAND_{BR,OR}_PRELIM for defining CONFIG_SYS_{BR,OR}{0,1}_PRELIM. After Kconfig migration, replacing some lines in the defconfig will have the same effect. Hence, we will not create distinct ve8313_{NOR,NAND} configs for such a small change. Instead, fix the current default (NOR first, NAND second), and unroll the CONFIG_SYS_NAND_{BR,OR}_PRELIM options. This will ease the Kconfig migration. Signed-off-by: Mario Six --- include/configs/MPC8315ERDB.h | 40 +++++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 64967f6798..7607704411 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -194,20 +194,6 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) -#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -239,13 +225,26 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* 8 bit port */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM \ - (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM \ + (OR_AM_32KB \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -254,10 +253,9 @@ | OR_FCM_EHTR) /* 0xFFFF8396 */ -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)