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Wed, 26 Sep 2018 13:48:22 +0000 From: Peng Fan To: sbabic@denx.de, agust@denx.de Date: Wed, 26 Sep 2018 21:52:49 +0800 Message-Id: <20180926135256.2098-26-peng.fan@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180926135256.2098-1-peng.fan@nxp.com> References: <20180926135256.2098-1-peng.fan@nxp.com> MIME-Version: 1.0 X-Originating-IP: [92.121.68.129] X-ClientProxiedBy: HK0PR01CA0053.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::17) To AM0PR04MB4482.eurprd04.prod.outlook.com (2603:10a6:208:73::16) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 942cbddb-1fa0-4921-e11e-08d623b6baab X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4482; X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4482; 3:Gh5uff7tTU42yZ5vzzGw6r+EO0WFJl7I0GiEc/xKUnlZmqqxwyLpeW/mxQLxbMKkSzLkf4mku+86OIgKoqfor60f1hTuh4Rxslna1sDvIWwdYvWBUWf73C1v170g1ieyu3R0CWqeVuzhuCwq9YFsdI6GBe7kvQokmdVOhuPly+0YNkwMlhizO18VPkcf/IghYfOgcMzK7K00iIyOFrP3YNzYXb0iIlzBe7aNvF6Ou2PyEWfer9J01/OWk3S0w8E6; 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AM0PR04MB4482; 6:ADZOwGH9alHqmddNti05PUUCNTW9z3LYveJNT+UuKnN2hSLsoGQI9i3cSyu/4yoJS/aOoKAtziTit+hGwnhTb/R1xM3/b4PeLJHMIiAOQk5rZZFlm1baCezLvrhstoDDrkLelvUkARI8CmUzHwwkxJ0EilmBaNuazqTXbTHpX9BQO/GGWT2ewC0YLvNlwJtcydweKYJ4qDcz4r8bHoHOTKm9nSFxQbrHAo87SlqT1v2kDSEhhLG8/4qFWRdbVlGwJ+1E/nWODnWWBx5WK8gALTc2nrqO7CBGfAJ5+uaSW2tCIE1LrPNYKHIte5S48uFeHedTTBmUpZA3ipGLJp1tah8NfwRV0a7gpMNHo+WI+t/oEa1Ls1TeZIQ6NrWXGYQQGqJtPxJ2TdsWMQrH1xzU0UR8bvZwq6gbFw/yeW+fRvQOzKw/TMho4wh+O0lH7WSP6vc0+OUmiCaOfdRKfUE9AQ==; 5:g9SUJXC/OsRnnl5aWFQcLQnTwPmt6q5509/NKArCZgBXIGFx70W2oHpyo3saTn84dkg9L6rL+5QA2Wdc5rawRn2wmqe5czux/p2mTCF24Ns3n2mTp6VKAhXdtoDLl29R2httDGaBcrUnfJpnlBeGMcTb1fmNsoqvNtp4NUYDOm8=; 7:ZB8ZuJdsSFCLlrXAFYxIUxB9wweBioeqdQ/TkFG8Xu6uh7Pqm/PAomcAuIj0UuxNhPrRCTgpMpPMC+5zhpe4IeHnK8+kN3Mr1qGZaBucB7S08kPGAm+CMUDU0QYHuJldfTKzmGeNeR11U6fQzJqwdm5K+r1ThF/RjTm6VN++S/28ufgn1GoIHdlQVwLVe7YhOT65m9Qa6l2lxB+lCTf65NmqwFhGPFgB87hDDaBYbefciNEETteWdhHy0hKoqIDn SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2018 13:48:22.0787 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 942cbddb-1fa0-4921-e11e-08d623b6baab X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4482 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V5 25/32] clk: imx: add clk driver for i.MX8QXP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add clk driver for i.MX8QXP, support clk enable/disable/get_rate/set_rate operations. Signed-off-by: Peng Fan Cc: Stefano Babic --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/imx/Kconfig | 6 ++ drivers/clk/imx/Makefile | 5 ++ drivers/clk/imx/clk-imx8.c | 212 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 225 insertions(+) create mode 100644 drivers/clk/imx/Kconfig create mode 100644 drivers/clk/imx/Makefile create mode 100644 drivers/clk/imx/clk-imx8.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c996d6574b..ce62ca8771 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -93,6 +93,7 @@ config CLK_STM32MP1 source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" +source "drivers/clk/imx/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 11468f2ee6..ef84b068a1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o +obj-y += imx/ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MESON) += clk_meson.o diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig new file mode 100644 index 0000000000..a6fb58d6cf --- /dev/null +++ b/drivers/clk/imx/Kconfig @@ -0,0 +1,6 @@ +config CLK_IMX8 + bool "Clock support for i.MX8" + depends on ARCH_IMX8 + select CLK + help + This enables support clock driver for i.MX8 platforms. diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile new file mode 100644 index 0000000000..5505ae52e2 --- /dev/null +++ b/drivers/clk/imx/Makefile @@ -0,0 +1,5 @@ +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_CLK_IMX8) += clk-imx8.o diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c new file mode 100644 index 0000000000..ba87ad6964 --- /dev/null +++ b/drivers/clk/imx/clk-imx8.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP + * Peng Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static ulong imx8_clk_get_rate(struct clk *clk) +{ + sc_pm_clk_t pm_clk; + ulong rate; + u16 resource; + int ret; + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case IMX8QXP_A35_DIV: + resource = SC_R_A35; + pm_clk = SC_PM_CLK_CPU; + break; + case IMX8QXP_SDHC0_IPG_CLK: + case IMX8QXP_SDHC0_CLK: + case IMX8QXP_SDHC0_DIV: + resource = SC_R_SDHC_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC1_IPG_CLK: + case IMX8QXP_SDHC1_CLK: + case IMX8QXP_SDHC1_DIV: + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART0_IPG_CLK: + case IMX8QXP_UART0_CLK: + resource = SC_R_UART_0; + pm_clk = SC_PM_CLK_PER; + break; + default: + dev_err(dev, "%s(Invalid #%ld)\n", __func__, clk->id); + return -EINVAL; + }; + + ret = sc_pm_get_clock_rate(-1, resource, pm_clk, + (sc_pm_clock_rate_t *)&rate); + if (ret) + printf("%s err %d\n", __func__, ret); + + return rate; +} + +static ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) +{ + sc_pm_clk_t pm_clk; + u32 new_rate = rate; + u16 resource; + int ret; + + debug("%s(#%ld), rate: %lu\n", __func__, clk->id, rate); + + switch (clk->id) { + case IMX8QXP_UART0_CLK: + resource = SC_R_UART_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART1_CLK: + resource = SC_R_UART_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART2_CLK: + resource = SC_R_UART_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART3_CLK: + resource = SC_R_UART_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC0_IPG_CLK: + case IMX8QXP_SDHC0_CLK: + case IMX8QXP_SDHC0_DIV: + resource = SC_R_SDHC_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC1_SEL: + case IMX8QXP_SDHC0_SEL: + return 0; + case IMX8QXP_SDHC1_IPG_CLK: + case IMX8QXP_SDHC1_CLK: + case IMX8QXP_SDHC1_DIV: + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; + default: + printf("%s %ld\n", __func__, clk->id); + return -EINVAL; + }; + + ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate); + if (ret) + printf("%s err %d\n", __func__, ret); + + return new_rate; +} + +static int __imx8_clk_enable(struct clk *clk, bool enable) +{ + sc_pm_clk_t pm_clk; + u16 resource; + int ret; + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case IMX8QXP_I2C0_CLK: + resource = SC_R_I2C_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C1_CLK: + resource = SC_R_I2C_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C2_CLK: + resource = SC_R_I2C_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C3_CLK: + resource = SC_R_I2C_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART0_CLK: + resource = SC_R_UART_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART1_CLK: + resource = SC_R_UART_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART2_CLK: + resource = SC_R_UART_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART3_CLK: + resource = SC_R_UART_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC0_IPG_CLK: + case IMX8QXP_SDHC0_CLK: + case IMX8QXP_SDHC0_DIV: + resource = SC_R_SDHC_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC1_IPG_CLK: + case IMX8QXP_SDHC1_CLK: + case IMX8QXP_SDHC1_DIV: + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; + default: + printf("%s not valid resource\n", __func__); + return -EINVAL; + } + + ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0); + if (ret) + printf("%s err %d\n", __func__, ret); + + return ret; +} + +static int imx8_clk_disable(struct clk *clk) +{ + return __imx8_clk_enable(clk, 0); +} + +static int imx8_clk_enable(struct clk *clk) +{ + return __imx8_clk_enable(clk, 1); +} + +static struct clk_ops imx8_clk_ops = { + .set_rate = imx8_clk_set_rate, + .get_rate = imx8_clk_get_rate, + .enable = imx8_clk_enable, + .disable = imx8_clk_disable, +}; + +static int imx8_clk_probe(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id imx8_clk_ids[] = { + { .compatible = "fsl,imx8qxp-clk" }, + { }, +}; + +U_BOOT_DRIVER(imx8_clk) = { + .name = "clk_imx8", + .id = UCLASS_CLK, + .of_match = imx8_clk_ids, + .ops = &imx8_clk_ops, + .probe = imx8_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +};