From patchwork Sun Aug 19 13:57:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 959375 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="dV+vKb4D"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41tfYR3FFFz9s3Z for ; Mon, 20 Aug 2018 00:32:59 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1AEF9C21E7D; Sun, 19 Aug 2018 14:12:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8014CC21F1A; Sun, 19 Aug 2018 14:03:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 351ECC21EDC; Sun, 19 Aug 2018 14:00:50 +0000 (UTC) Received: from mail-pf1-f193.google.com (mail-pf1-f193.google.com [209.85.210.193]) by lists.denx.de (Postfix) with ESMTPS id CDEFBC21E7F for ; Sun, 19 Aug 2018 14:00:46 +0000 (UTC) Received: by mail-pf1-f193.google.com with SMTP id b11-v6so5501173pfo.3 for ; Sun, 19 Aug 2018 07:00:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pGfdArz2K3ge8obduPw8mUyU2HZ31EM+wEYQFwaEGc4=; b=dV+vKb4DuWT8gdlzsvTBPAmjRRM4wMPhVk2uM9vaQHB8d8LlxKQ3oFrhHBAtfXCxh3 m3mumf5YjjqvLH+CPMh+jurauSL1sgta6zsWmu03aMYyx6VslB4sADgZI4flIISx89ag D4JLefyA8U1nows63sLqIFVHt8pyJj4OIW9AY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pGfdArz2K3ge8obduPw8mUyU2HZ31EM+wEYQFwaEGc4=; b=cePyhfQXdrApObhi7M1g9IXRZFxS0wRLtJYUCc2HEITrU2mHadANFR1JBiXg8zw6WM /kIYUgJNrRalrSPjraDpA5tGv127OV+0o1gF7fnR5e6Pw5NAilUQ1cpNRonZgNYhy07n 7AKA24XzWxC5UYCq9+7aaBvL1R9X8wqRR2bq/uSmMhc+iaT3FX+oTUFDb9c0hiceVwG9 zwqhatCmiKGAnMBIc+zVdGzW/2Fb7Z0i/62kJ2gS8SFhYaMPwLqkf7QzOazexEKJ6Ygk XlcNVTDcz0+oE56CTcQUMPCNuST2zQLSBmi4S9tgDgMww6Cy/vzHdE36bqrZMYm5fXp3 wWZA== X-Gm-Message-State: AOUpUlENlFegvhJtlANtn3kWaCEaN5g4p6LPkvDSDdAIH+Qm5YpzRnwT nH5oPZnOzNG2sd/KjS7+EFQqRg== X-Google-Smtp-Source: AA+uWPwhL0+DmPS4zIByktOKKdWdgZs75VgTkpqLiGtzAQDOyFfbpQ2Lp8TDOalZJhZTumjT3R1p4g== X-Received: by 2002:a62:1756:: with SMTP id 83-v6mr44875227pfx.217.1534687245385; Sun, 19 Aug 2018 07:00:45 -0700 (PDT) Received: from localhost.localdomain ([106.208.36.229]) by smtp.gmail.com with ESMTPSA id l185-v6sm8902816pga.65.2018.08.19.07.00.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Aug 2018 07:00:44 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara , Chen-Yu Tsai , Icenowy Zheng Date: Sun, 19 Aug 2018 19:27:03 +0530 Message-Id: <20180819135715.15799-47-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20180819135715.15799-1-jagan@amarulasolutions.com> References: <20180819135715.15799-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 46/58] clk: sunxi: Implement UART clocks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement UART clocks for all Allwinner SoC clock drivers via clock map descriptor table. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/clk_a10.c | 9 +++++++++ drivers/clk/sunxi/clk_a10s.c | 5 +++++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 7 +++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 5 +++++ drivers/clk/sunxi/clk_r40.c | 9 +++++++++ drivers/clk/sunxi/clk_v3s.c | 4 ++++ 9 files changed, 57 insertions(+) diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index ee499c402a..d145d37217 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -27,6 +27,15 @@ static struct ccu_clk_map a10_clks[] = { [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL }, [CLK_AHB_SPI3] = { 0x060, BIT(23), NULL }, + [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_APB1_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_APB1_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_APB1_UART5] = { 0x06c, BIT(21), NULL }, + [CLK_APB1_UART6] = { 0x06c, BIT(22), NULL }, + [CLK_APB1_UART7] = { 0x06c, BIT(23), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index bca248f59f..5912043f19 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -23,6 +23,11 @@ static struct ccu_clk_map a10s_clks[] = { [CLK_AHB_SPI1] = { 0x060, BIT(21), NULL }, [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL }, + [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_APB1_UART3] = { 0x06c, BIT(19), NULL }, + #ifdef CONFIG_MMC [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 183c6275f3..331c79af81 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = { [CLK_BUS_EHCI] = { 0x060, BIT(26), NULL }, [CLK_BUS_OHCI] = { 0x060, BIT(29), NULL }, + [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + #ifdef CONFIG_MMC [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index a5c6628c63..40803a1d64 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -28,6 +28,13 @@ static struct ccu_clk_map a31_clks[] = { [CLK_AHB1_OHCI1] = { 0x060, BIT(30), NULL }, [CLK_AHB1_OHCI2] = { 0x060, BIT(31), NULL }, + [CLK_APB2_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_APB2_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_APB2_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_APB2_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_APB2_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_APB2_UART5] = { 0x06c, BIT(21), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 218d4f09ea..13b506f983 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -24,6 +24,12 @@ static struct ccu_clk_map a64_clks[] = { [CLK_BUS_OHCI0] = { 0x060, BIT(28), NULL }, [CLK_BUS_OHCI1] = { 0x060, BIT(29), NULL }, + [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 47b7672e7f..5c1235fa7b 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -21,6 +21,12 @@ static struct ccu_clk_map a83t_clks[] = { [CLK_BUS_EHCI1] = { 0x060, BIT(27), NULL }, [CLK_BUS_OHCI0] = { 0x060, BIT(29), NULL }, + [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f610cee745..b132ae0a0d 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -28,6 +28,11 @@ static struct ccu_clk_map h3_clks[] = { [CLK_BUS_OHCI2] = { 0x060, BIT(30), NULL }, [CLK_BUS_OHCI3] = { 0x060, BIT(31), NULL }, + [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 24c26ad3be..1e5b1d10f7 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -25,6 +25,15 @@ static struct ccu_clk_map r40_clks[] = { [CLK_BUS_OHCI1] = { 0x060, BIT(30), NULL }, [CLK_BUS_OHCI2] = { 0x060, BIT(31), NULL }, + [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_BUS_UART5] = { 0x06c, BIT(21), NULL }, + [CLK_BUS_UART6] = { 0x06c, BIT(22), NULL }, + [CLK_BUS_UART7] = { 0x06c, BIT(23), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index ae4f6ee066..c6e57147ee 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -19,6 +19,10 @@ static struct ccu_clk_map v3s_clks[] = { [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(24), NULL }, + [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },