From patchwork Sun Aug 19 13:56:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 959340 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="MXDZ/3TP"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41tf6q1DLnz9ryn for ; Mon, 20 Aug 2018 00:13:23 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D170BC21E88; Sun, 19 Aug 2018 14:12:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 825BAC21F13; Sun, 19 Aug 2018 14:04:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 074D9C21EBA; Sun, 19 Aug 2018 14:00:40 +0000 (UTC) Received: from mail-pl0-f65.google.com (mail-pl0-f65.google.com [209.85.160.65]) by lists.denx.de (Postfix) with ESMTPS id 15F2AC21E3E for ; Sun, 19 Aug 2018 14:00:30 +0000 (UTC) Received: by mail-pl0-f65.google.com with SMTP id u11-v6so5819967plq.5 for ; Sun, 19 Aug 2018 07:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W/8clBWkABhqmne61nvD7p1/HUjSzGdi57woQwPfvoY=; b=MXDZ/3TP/0J4H+asZ4iEyO/Mq30kX/HmhGcAH+J1jaKGNNlPwiUeIKZgjaHBzCLWHa fqQSpEzYIIh4HsogSIS4XVsgqEo8A3FTHCAcmeHrakSx42xRSwyvJS5FCm6hOsCjiWLp OQ7zb5I338LaxIdMIfZdja8H3qAkcUu1UiNOQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W/8clBWkABhqmne61nvD7p1/HUjSzGdi57woQwPfvoY=; b=cUpfgMcrxXwZRJTWR17Q1h8W73/WL2w4ZHE3+1c4hG2tlBhbjPoUENZCRUZB6hV4EB lCMjV3gY+2WghQoRxJXyEk0vSC7PBRKnvRRewFPWHFWshgx2phkDNAuzi6+nO2fadbwT y5HEGJYYe+YIL7PfJOvdY9Qh4juKbYzs6z0B4R5xwCnu0kxe6SElhvcTkU6MkaNy51Xr HoahYwGxm3E2RKgvQbj12saW+rWdzsFEInM8qJ/7M6zWRe8d+ot7VtIRHQPpYFTAoLh2 TVbL16gWcW4d8amdbq1blzKjSNmP1gx/MgQH8LG5tpvnEinc521yCoK1Gc4ZTzgQpDhn 4ZHg== X-Gm-Message-State: AOUpUlHFTOzZhgoRNWEhTX1fsevL+T1wTd+ZCCRHn0HFScezHPW2YCwX maCo7ejILfwY6xx2kkVP0Ajiwg== X-Google-Smtp-Source: AA+uWPyLlmpazLSupUyNjnwHNWWgmR6/hrSziJC/KxYQR8CgdBmxgwcNYBJvHo00RvmXeRvB4JjwKA== X-Received: by 2002:a17:902:6b89:: with SMTP id p9-v6mr41385316plk.272.1534687228673; Sun, 19 Aug 2018 07:00:28 -0700 (PDT) Received: from localhost.localdomain ([106.208.36.229]) by smtp.gmail.com with ESMTPSA id l185-v6sm8902816pga.65.2018.08.19.07.00.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Aug 2018 07:00:28 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara , Chen-Yu Tsai , Icenowy Zheng Date: Sun, 19 Aug 2018 19:26:59 +0530 Message-Id: <20180819135715.15799-43-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20180819135715.15799-1-jagan@amarulasolutions.com> References: <20180819135715.15799-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 42/58] clk: sunxi: Implement SPI clocks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement SPI AHB and MOD clocks for all Allwinner SoC clock drivers via clock map descriptor table. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/clk_a10.c | 9 +++++++++ drivers/clk/sunxi/clk_a10s.c | 7 +++++++ drivers/clk/sunxi/clk_a31.c | 9 +++++++++ drivers/clk/sunxi/clk_a64.c | 5 +++++ drivers/clk/sunxi/clk_h3.c | 5 +++++ drivers/clk/sunxi/clk_v3s.c | 3 +++ 6 files changed, 38 insertions(+) diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index 55176bc174..ee499c402a 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -22,12 +22,21 @@ static struct ccu_clk_map a10_clks[] = { [CLK_AHB_MMC1] = { 0x060, BIT(9), NULL }, [CLK_AHB_MMC2] = { 0x060, BIT(10), NULL }, [CLK_AHB_MMC3] = { 0x060, BIT(11), NULL }, + [CLK_AHB_SPI0] = { 0x060, BIT(20), NULL }, + [CLK_AHB_SPI1] = { 0x060, BIT(21), NULL }, + [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL }, + [CLK_AHB_SPI3] = { 0x060, BIT(23), NULL }, [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, [CLK_MMC3] = { 0x094, BIT(31), &mmc_clk_set_rate }, + [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_SPI1] = { 0x0a4, BIT(31), NULL }, + [CLK_SPI2] = { 0x0a8, BIT(31), NULL }, + [CLK_SPI3] = { 0x0d4, BIT(31), NULL }, + [CLK_USB_OHCI0] = { 0x0cc, BIT(6), NULL }, [CLK_USB_OHCI1] = { 0x0cc, BIT(7), NULL }, [CLK_USB_PHY] = { 0x0cc, BIT(8), NULL }, diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index fbac0ad751..bca248f59f 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -19,6 +19,9 @@ static struct ccu_clk_map a10s_clks[] = { [CLK_AHB_MMC0] = { 0x060, BIT(8), NULL }, [CLK_AHB_MMC1] = { 0x060, BIT(9), NULL }, [CLK_AHB_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_AHB_SPI0] = { 0x060, BIT(20), NULL }, + [CLK_AHB_SPI1] = { 0x060, BIT(21), NULL }, + [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL }, #ifdef CONFIG_MMC [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, @@ -26,6 +29,10 @@ static struct ccu_clk_map a10s_clks[] = { [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, #endif + [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_SPI1] = { 0x0a4, BIT(31), NULL }, + [CLK_SPI2] = { 0x0a8, BIT(31), NULL }, + [CLK_USB_OHCI] = { 0x0cc, BIT(6), NULL }, [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 15076d0e72..1fa77e1272 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -17,6 +17,10 @@ static struct ccu_clk_map a31_clks[] = { [CLK_AHB1_MMC1] = { 0x060, BIT(9), NULL }, [CLK_AHB1_MMC2] = { 0x060, BIT(10), NULL }, [CLK_AHB1_MMC3] = { 0x060, BIT(12), NULL }, + [CLK_AHB1_SPI0] = { 0x060, BIT(20), NULL }, + [CLK_AHB1_SPI1] = { 0x060, BIT(21), NULL }, + [CLK_AHB1_SPI2] = { 0x060, BIT(22), NULL }, + [CLK_AHB1_SPI3] = { 0x060, BIT(23), NULL }, [CLK_AHB1_OTG] = { 0x060, BIT(24), NULL }, [CLK_AHB1_EHCI0] = { 0x060, BIT(26), NULL }, [CLK_AHB1_EHCI1] = { 0x060, BIT(27), NULL }, @@ -29,6 +33,11 @@ static struct ccu_clk_map a31_clks[] = { [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, [CLK_MMC3] = { 0x094, BIT(31), &mmc_clk_set_rate }, + [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_SPI1] = { 0x0a4, BIT(31), NULL }, + [CLK_SPI2] = { 0x0a8, BIT(31), NULL }, + [CLK_SPI3] = { 0x0ac, BIT(31), NULL }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_PHY2] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 9ef9b606d2..aa2e69d0a3 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -16,6 +16,8 @@ static struct ccu_clk_map a64_clks[] = { [CLK_BUS_MMC0] = { 0x060, BIT(8), NULL }, [CLK_BUS_MMC1] = { 0x060, BIT(9), NULL }, [CLK_BUS_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, + [CLK_BUS_SPI1] = { 0x060, BIT(21), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(23), NULL }, [CLK_BUS_EHCI0] = { 0x060, BIT(24), NULL }, [CLK_BUS_EHCI1] = { 0x060, BIT(25), NULL }, @@ -26,6 +28,9 @@ static struct ccu_clk_map a64_clks[] = { [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, + [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_SPI1] = { 0x0a4, BIT(31), NULL }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_HSIC] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index ad15aaae67..386289b654 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -16,6 +16,8 @@ static struct ccu_clk_map h3_clks[] = { [CLK_BUS_MMC0] = { 0x060, BIT(8), NULL }, [CLK_BUS_MMC1] = { 0x060, BIT(9), NULL }, [CLK_BUS_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, + [CLK_BUS_SPI1] = { 0x060, BIT(21), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(23), NULL }, [CLK_BUS_EHCI0] = { 0x060, BIT(24), NULL }, [CLK_BUS_EHCI1] = { 0x060, BIT(25), NULL }, @@ -30,6 +32,9 @@ static struct ccu_clk_map h3_clks[] = { [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, + [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_SPI1] = { 0x0a4, BIT(31), NULL }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_PHY2] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 6eeec201a2..1cca57e065 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -16,12 +16,15 @@ static struct ccu_clk_map v3s_clks[] = { [CLK_BUS_MMC0] = { 0x060, BIT(8), NULL }, [CLK_BUS_MMC1] = { 0x060, BIT(9), NULL }, [CLK_BUS_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(24), NULL }, [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, + [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, };