From patchwork Mon Aug 6 08:23:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Six X-Patchwork-Id: 953768 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gdsys.cc Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41kW4b3fx8z9s5H for ; Mon, 6 Aug 2018 18:28:15 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1ACC7C21DDC; Mon, 6 Aug 2018 08:27:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8843CC21E31; Mon, 6 Aug 2018 08:24:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 34CA3C21D56; Mon, 6 Aug 2018 08:24:37 +0000 (UTC) Received: from smtprelay03.ispgateway.de (smtprelay03.ispgateway.de [80.67.29.28]) by lists.denx.de (Postfix) with ESMTPS id D7072C21C2F for ; Mon, 6 Aug 2018 08:24:36 +0000 (UTC) Received: from [80.151.34.241] (helo=bob3.testumgebung.local) by smtprelay03.ispgateway.de with esmtpa (Exim 4.90_1) (envelope-from ) id 1fmaod-0002pz-SD; Mon, 06 Aug 2018 10:24:35 +0200 From: Mario Six To: U-Boot Mailing List , Simon Glass Date: Mon, 6 Aug 2018 10:23:38 +0200 Message-Id: <20180806082346.21211-9-mario.six@gdsys.cc> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180806082346.21211-1-mario.six@gdsys.cc> References: <20180806082346.21211-1-mario.six@gdsys.cc> X-Df-Sender: bWFyaW8uc2l4QGdkc3lzLmNj Subject: [U-Boot] [PATCH v4 09/17] timer: Add MPC83xx timer driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six --- Notes: v3 -> v4: * Removed superfluous get_timer (switched to usage of standard function) * Improved error handling and debug reporting * Added full documentation v2 -> v3: * Got rid of the static variables * Added driver files to MAINTAINERS v1 -> v2: * Removed now-superfluous comments * Removed usage of uclass_{first,next}_device_compat * Switched to usage of new board uclass (instead of devinfo) .../bindings/timer/fsl,mpc83xx-timer.txt | 21 ++ MAINTAINERS | 1 + arch/powerpc/cpu/mpc83xx/cpu.c | 4 +- arch/powerpc/lib/Makefile | 4 + arch/powerpc/lib/interrupts.c | 5 +- drivers/timer/Kconfig | 7 + drivers/timer/Makefile | 1 + drivers/timer/mpc83xx_timer.c | 249 +++++++++++++++++++++ 8 files changed, 289 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt create mode 100644 drivers/timer/mpc83xx_timer.c diff --git a/Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt b/Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt new file mode 100644 index 00000000000..608d24110ba --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt @@ -0,0 +1,21 @@ +MPC83xx timer devices + +MPC83xx SoCs offer a decrementer interrupt that can be used to implement delay +functionality, and periodically triggered actions. + +Required properties: +- compatible: must be "fsl,mpc83xx-timer" +- clocks: must be a reference to the system's CSB (coherent system bus) clock, + provided by one of the "fsl,mpc83xx-clk" devices + +Example: + +socclocks: clocks { + compatible = "fsl,mpc832x-clk"; + #clock-cells = <1>; +}; + +timer { + compatible = "fsl,mpc83xx-timer"; + clocks = <&socclocks MPC83XX_CLK_CSB>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index 7710989ea4f..58a8f8da7ba 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -502,6 +502,7 @@ F: drivers/sysreset/sysreset_mpc83xx.h F: drivers/clk/mpc83xx_clk.c F: drivers/clk/mpc83xx_clk.h F: include/dt-bindings/clk/mpc83xx-clk.h +F: drivers/timer/mpc83xx_timer.c F: arch/powerpc/cpu/mpc83xx/ F: arch/powerpc/include/asm/arch-mpc83xx/ diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index e1d2f2f07cb..ffb42415feb 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -175,12 +175,12 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) /* * Get timebase clock frequency (like cpu_clk in Hz) */ - +#ifndef CONFIG_TIMER unsigned long get_tbclk(void) { return (gd->bus_clk + 3L) / 4L; } - +#endif #if defined(CONFIG_WATCHDOG) void watchdog_reset (void) diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index c3acefaea7e..8ac49bdd060 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -17,13 +17,17 @@ endif ifdef MINIMAL obj-y += cache.o time.o +ifndef CONFIG_TIMER obj-y += ticks.o +endif else obj-y += ppcstring.o obj-y += ppccache.o +ifndef CONFIG_TIMER obj-y += ticks.o +endif obj-y += reloc.o obj-$(CONFIG_BAT_RW) += bat_rw.o diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c index f63e5cf799b..19682cfcfad 100644 --- a/arch/powerpc/lib/interrupts.c +++ b/arch/powerpc/lib/interrupts.c @@ -14,6 +14,7 @@ #include #endif +#ifndef CONFIG_MPC83XX_TIMER #ifdef CONFIG_SHOW_ACTIVITY void board_show_activity (ulong) __attribute__((weak, alias("__board_show_activity"))); @@ -44,7 +45,7 @@ static __inline__ void set_dec (unsigned long val) if (val) asm volatile ("mtdec %0"::"r" (val)); } - +#endif /* !CONFIG_MPC83XX_TIMER */ void enable_interrupts (void) { @@ -60,6 +61,7 @@ int disable_interrupts (void) return ((msr & MSR_EE) != 0); } +#ifndef CONFIG_MPC83XX_TIMER int interrupt_init (void) { /* call cpu specific function from $(CPU)/interrupts.c */ @@ -102,3 +104,4 @@ ulong get_timer (ulong base) { return (timestamp - base); } +#endif /* !CONFIG_MPC83XX_TIMER */ diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 8a31397553d..c7909bd6e52 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -133,4 +133,11 @@ config STM32_TIMER Select this to enable support for the timer found on STM32 devices. +config MPC83XX_TIMER + bool "MPC83xx timer support" + depends on TIMER + help + Select this to enable support for the timer found on + devices based on the MPC83xx family of SoCs. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 71c54048540..bcc14342b1a 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o +obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c new file mode 100644 index 00000000000..84a9ab072a9 --- /dev/null +++ b/drivers/timer/mpc83xx_timer.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * struct mpc83xx_timer_priv - Private data structure for MPC83xx timer driver + * @decrementer_count: Value to which the decrementer register should be re-set + * to when a timer interrupt occurs, thus determines the + * interrupt frequency (value for 1e6/HZ microseconds) + * @timestamp: Counter for the number of timer interrupts that have + * occurred (i.e. can be used to trigger events + * periodically in the timer interrupt) + */ +struct mpc83xx_timer_priv { + uint decrementer_count; + ulong timestamp; +}; + +/* + * Bitmask for enabling the time base in the SPCR (System Priority + * Configuration Register) + */ +static const u32 SPCR_TBEN_MASK = BIT(31 - 9); + +/** + * get_dec() - Get the value of the decrementer register + * + * Return: The value of the decrementer register + */ +static inline unsigned long get_dec(void) +{ + unsigned long val; + + asm volatile ("mfdec %0" : "=r" (val) : ); + + return val; +} + +/** + * set_dec() - Set the value of the decrementer register + * @val: The value of the decrementer register to be set + */ +static inline void set_dec(unsigned long val) +{ + if (val) + asm volatile ("mtdec %0"::"r" (val)); +} + +/** + * mftbu() - Get value of TBU (upper time base) register + * + * Return: Value of the TBU register + */ +static inline u32 mftbu(void) +{ + u32 rval; + + asm volatile("mftbu %0" : "=r" (rval)); + return rval; +} + +/** + * mftb() - Get value of TBL (lower time base) register + * + * Return: Value of the TBL register + */ +static inline u32 mftb(void) +{ + u32 rval; + + asm volatile("mftb %0" : "=r" (rval)); + return rval; +} + +/* + * TODO(mario.six@gdsys.cc): This should really be done by timer_init, and the + * interrupt init should go into a interrupt driver. + */ +int interrupt_init(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + struct udevice *csb; + struct udevice *board; + struct udevice *timer; + struct mpc83xx_timer_priv *timer_priv; + struct clk clock; + int ret; + + ret = uclass_first_device_err(UCLASS_TIMER, &timer); + if (ret) { + debug("%s: Could not find timer device (error: %d)", + __func__, ret); + return ret; + } + + timer_priv = dev_get_priv(timer); + + if (board_get(&board)) { + debug("%s: board device could not be fetched.\n", __func__); + return -ENOENT; + } + + ret = uclass_get_device_by_phandle(UCLASS_SIMPLE_BUS, board, + "csb", &csb); + if (ret) { + debug("%s: Could not retrieve CSB device (error: %d)", + __func__, ret); + return ret; + } + + ret = clk_get_by_index(csb, 0, &clock); + if (ret) { + debug("%s: Could not retrieve clock (error: %d)", + __func__, ret); + return ret; + } + + timer_priv->decrementer_count = (clk_get_rate(&clock) / 4) + / CONFIG_SYS_HZ; + /* Enable e300 time base */ + setbits_be32(&immr->sysconf.spcr, SPCR_TBEN_MASK); + + set_dec(timer_priv->decrementer_count); + + /* Switch on interrupts */ + set_msr(get_msr() | MSR_EE); + + return 0; +} + +/** + * timer_interrupt() - Handler for the timer interrupt + * @regs: Array of register values + */ +void timer_interrupt(struct pt_regs *regs) +{ + struct udevice *timer = gd->timer; + struct mpc83xx_timer_priv *priv; + + /* + * During initialization, gd->timer might not be set yet, but the timer + * interrupt may already be enabled. In this case, wait for the + * initialization to complete + */ + if (!timer) + return; + + priv = dev_get_priv(timer); + + /* Restore Decrementer Count */ + set_dec(priv->decrementer_count); + + priv->timestamp++; + +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) + if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) + WATCHDOG_RESET(); +#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ + +#ifdef CONFIG_LED_STATUS + status_led_tick(priv->timestamp); +#endif /* CONFIG_LED_STATUS */ + +#ifdef CONFIG_SHOW_ACTIVITY + board_show_activity(priv->timestamp); +#endif /* CONFIG_SHOW_ACTIVITY */ +} + +void wait_ticks(ulong ticks) +{ + ulong end = get_ticks() + ticks; + + while (end > get_ticks()) + WATCHDOG_RESET(); +} + +static int mpc83xx_timer_get_count(struct udevice *dev, u64 *count) +{ + u32 tbu, tbl; + + /* + * To make sure that no tbl overflow occurred between reading tbl and + * tbu, read tbu again, and compare it with the previously read tbu + * value: If they're different, a tbl overflow has occurred. + */ + do { + tbu = mftbu(); + tbl = mftb(); + } while (tbu != mftbu()); + + *count = (tbu * 0x10000ULL) + tbl; + + return 0; +} + +static int mpc83xx_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev->uclass_priv; + struct clk clock; + int ret; + + ret = interrupt_init(); + if (ret) { + debug("%s: interrupt_init failed (err = %d)\n", + dev->name, ret); + return ret; + } + + ret = clk_get_by_index(dev, 0, &clock); + if (ret) { + debug("%s: Could not retrieve clock (err = %d)\n", + dev->name, ret); + return ret; + } + + uc_priv->clock_rate = (clk_get_rate(&clock) + 3L) / 4L; + + return 0; +} + +static const struct timer_ops mpc83xx_timer_ops = { + .get_count = mpc83xx_timer_get_count, +}; + +static const struct udevice_id mpc83xx_timer_ids[] = { + { .compatible = "fsl,mpc83xx-timer" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mpc83xx_timer) = { + .name = "mpc83xx_timer", + .id = UCLASS_TIMER, + .of_match = mpc83xx_timer_ids, + .probe = mpc83xx_timer_probe, + .ops = &mpc83xx_timer_ops, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto_alloc_size = sizeof(struct mpc83xx_timer_priv), +};