From patchwork Mon Jul 16 11:28:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944335 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="KB2c3blu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThQd2Y9gz9ryt for ; Mon, 16 Jul 2018 21:44:25 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E8D35C220A3; Mon, 16 Jul 2018 11:42:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2CC72C220F4; Mon, 16 Jul 2018 11:31:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 63E70C221AC; Mon, 16 Jul 2018 11:30:28 +0000 (UTC) Received: from mail-pf0-f195.google.com (mail-pf0-f195.google.com [209.85.192.195]) by lists.denx.de (Postfix) with ESMTPS id ED7C0C21E42 for ; Mon, 16 Jul 2018 11:30:13 +0000 (UTC) Received: by mail-pf0-f195.google.com with SMTP id q7-v6so25025858pff.2 for ; Mon, 16 Jul 2018 04:30:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HDKUKq4x52XHUMVo4FpDihZUmG8cdg5P0QYH9eT/mYU=; b=KB2c3blu/wjE3HJNKWY/Jc4HOeZCRPLNofgV/1bBK8mSo+brAhuXnvoLclYgRIAgpF d/DNg5t1/mD3xy+BRSdIuMF9OAir6qJ6krqIMdPGUEZTEeIJUz4CZi65mgr0E2E/JduN Jo7LAK8F7IjZFf4K/rjUHsquCVQF2ME+f3KNw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HDKUKq4x52XHUMVo4FpDihZUmG8cdg5P0QYH9eT/mYU=; b=oAOq/CNe14VMVXR9dou7C90wMATLqtfbGipV0uFH9m1hczk/n5H1o840Ys3a6UXbEg zscVOpGHGcI+nzmj75lZ5xael5uO/N6ydnSCp69VGA4qEm++7BJPgP1L6sB7dh1q4YMX gNww5uB5t1CdHuRbTse02WmW+fyfr8wXbO0at275872tD8Y1eEYUeosQUj/w8vt9Eb7Y h0ypF+QMQEx5WeYhbmUsdAP3WTZrENV0WBUitntJ76ZZEeoRnMejfjZhfFgWsN0zSIvA 7BJLlmiGqMCvSjygFH4gJBsm+xTBKrrvDJFUCag1ACCk8565AJy8D8IsLe64HYxWWscY e5AA== X-Gm-Message-State: AOUpUlG9NqFxT/ySiS4DgsSOw5cOlr3uUOKtmpJdiQqc4pww5wEotm2l G7xRF7rw1ZdqdwBLQ0Q6knPPZg== X-Google-Smtp-Source: AAOMgpfsuPEsJ+9n3T/iFECE8Et20S9/mBOnN6qBQXgSIZEEQ1i+JhscRB4qK1/EaSrtpdEkRIQYzw== X-Received: by 2002:a62:828a:: with SMTP id w132-v6mr17646786pfd.121.1531740612581; Mon, 16 Jul 2018 04:30:12 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.30.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:30:12 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:41 +0530 Message-Id: <20180716112850.3961-27-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 26/35] reset: sunxi: Add initial RESET driver for A23 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial reset driver Allwinner A23. Implemented reset deassert and assert functions for USB OHCI, EHCI, OTG and PHY bus reset and clock registers. Signed-off-by: Jagan Teki --- drivers/reset/sunxi/Kconfig | 7 ++ drivers/reset/sunxi/Makefile | 1 + drivers/reset/sunxi/reset_a23.c | 111 ++++++++++++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 drivers/reset/sunxi/reset_a23.c diff --git a/drivers/reset/sunxi/Kconfig b/drivers/reset/sunxi/Kconfig index bf1a2f05bf..6eb6a73205 100644 --- a/drivers/reset/sunxi/Kconfig +++ b/drivers/reset/sunxi/Kconfig @@ -30,6 +30,13 @@ config RESET_SUN6I_A31 This enables common reset driver support for platforms based on Allwinner A31/A31s SoC. +config RESET_SUN8I_A23 + bool "Reset driver for Allwinner A23" + default MACH_SUN8I_A23 + help + This enables common reset driver support for platforms based + on Allwinner A23 SoC. + config RESET_SUN8I_H3 bool "Reset driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile index b599e1994b..97452a275c 100644 --- a/drivers/reset/sunxi/Makefile +++ b/drivers/reset/sunxi/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_RESET_SUN4I_A10) += reset_a10.o obj-$(CONFIG_RESET_SUN5I_A10S) += reset_a10s.o obj-$(CONFIG_RESET_SUN6I_A31) += reset_a31.o +obj-$(CONFIG_RESET_SUN8I_A23) += reset_a23.o obj-$(CONFIG_RESET_SUN8I_H3) += reset_h3.o obj-$(CONFIG_RESET_SUN50I_A64) += reset_a64.o diff --git a/drivers/reset/sunxi/reset_a23.c b/drivers/reset/sunxi/reset_a23.c new file mode 100644 index 0000000000..2f315ff4bb --- /dev/null +++ b/drivers/reset/sunxi/reset_a23.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a23_reset_priv { + void *base; +}; + +static int a23_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + /* check dt-bindings/reset/sun8i-a23-ccu.h for max id */ + if (reset_ctl->id > 39) + return -EINVAL; + + return 0; +} + +static int a23_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + return 0; +} + +static int a23_reset_assert(struct reset_ctl *reset_ctl) +{ + struct a23_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + clrbits_le32(priv->base + 0xcc, BIT(reset_ctl->id)); + return 0; + case RST_BUS_OTG: + clrbits_le32(priv->base + 0x2c0, BIT(24)); + return 0; + case RST_BUS_EHCI: + clrbits_le32(priv->base + 0x2c0, BIT(26)); + return 0; + case RST_BUS_OHCI: + clrbits_le32(priv->base + 0x2c0, BIT(29)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +static int a23_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct a23_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(#%ld)\n", __func__, reset_ctl->id); + + switch (reset_ctl->id) { + case RST_USB_PHY0: + case RST_USB_PHY1: + setbits_le32(priv->base + 0xcc, BIT(reset_ctl->id)); + return 0; + case RST_BUS_OTG: + setbits_le32(priv->base + 0x2c0, BIT(24)); + return 0; + case RST_BUS_EHCI: + setbits_le32(priv->base + 0x2c0, BIT(26)); + return 0; + case RST_BUS_OHCI: + setbits_le32(priv->base + 0x2c0, BIT(29)); + return 0; + default: + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return -ENODEV; + } +} + +struct reset_ops a23_reset_ops = { + .request = a23_reset_request, + .free = a23_reset_free, + .rst_assert = a23_reset_assert, + .rst_deassert = a23_reset_deassert, +}; + +static int a23_reset_probe(struct udevice *dev) +{ + struct a23_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +U_BOOT_DRIVER(reset_sun8i_a23) = { + .name = "sun8i_a23_reset", + .id = UCLASS_RESET, + .ops = &a23_reset_ops, + .probe = a23_reset_probe, + .priv_auto_alloc_size = sizeof(struct a23_reset_priv), +};