From patchwork Mon Jul 16 11:28:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944353 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="TfwZP5BL"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThcV3lM1z9ryt for ; Mon, 16 Jul 2018 21:52:58 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 35A23C22126; Mon, 16 Jul 2018 11:40:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B6C1FC220C0; Mon, 16 Jul 2018 11:31:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C9241C220FE; Mon, 16 Jul 2018 11:30:13 +0000 (UTC) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by lists.denx.de (Postfix) with ESMTPS id 2464AC22132 for ; Mon, 16 Jul 2018 11:30:01 +0000 (UTC) Received: by mail-pg1-f196.google.com with SMTP id z14-v6so1094762pgv.12 for ; Mon, 16 Jul 2018 04:30:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uLyKQiQq/dN8x6SmsuVJvbQNTk1ApdxNbEBp2Yd3trI=; b=TfwZP5BLI1Ruw1RUjoS7l226w+Wb+LcmlS6E6mGZ2oiAyjaoi/vAmwqBvhz0x9Pyy2 9kNR+8jS3hHvVXg4a26kH0bhV85iiEwUr2yHAy4wSHL6IQ3ibMl+0OdjbgN76GDz9uQm JkyWQQG7JsAUhldEOita6feeNUzPDPMRm5aZM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uLyKQiQq/dN8x6SmsuVJvbQNTk1ApdxNbEBp2Yd3trI=; b=iMepX2KqVq7Qb750Ypj2+tP2vMoqg1aF2Q5U0VJQSSjHMa4HU3MctyMFgLJhju5kdT 9EoaAFxacuFGffLeA0FtoEwsl4W59JKn4KPU4Jjuw6bOKU00qeV/yuqT6AtRy6lmmXvo RmigETUcULpp8uxMF93yzvI1xaTeJK8q6q2mOgoxXPbduI5hUqY+qYcnD4ojaqEbHcMe W9CbNIAPC8zuZOMhhuLl4KAcBEXJSgEnKuScJoILV7iH5C5ni3OF718Kdjb0Q+TvQJHF T1xGJwi3uTDDxbYbsXOASbeWYtNVJznDBOq1WPi+l5LqRaxQiqoEVW6qGxiEdTk/o40/ c79A== X-Gm-Message-State: AOUpUlEUjKVwW5OFuiHDIEbd44tWgGKHfAaYkyxl20OR8ym0brXd4Mtn dVWEfJTtUhsegl7NvZ/KpMqKDA== X-Google-Smtp-Source: AAOMgpePINQ7NWN9SKpyIjO7exbbEA8b8N+nHKhN8gLaskewI6UIVyVSyFO3PWo6yG6DlqbZ4AvMZw== X-Received: by 2002:aa7:82c3:: with SMTP id f3-v6mr4638019pfn.136.1531740599733; Mon, 16 Jul 2018 04:29:59 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:59 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:36 +0530 Message-Id: <20180716112850.3961-22-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 21/35] clk: sunxi: Add initial CLK driver for A10s/A13 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial clock driver Allwinner for A10s/A13. Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 7 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a10s.c | 105 +++++++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a10s.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 36acfa1b88..6801b845cf 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -15,6 +15,13 @@ config CLK_SUN4I_A10 This enables common clock driver support for platforms based on Allwinner A10/A20 SoC. +config CLK_SUN5I_A10S + bool "Clock driver for Allwinner A10s/A13" + default MACH_SUN5I + help + This enables common clock driver support for platforms based + on Allwinner A10s/A13 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index bcf2c4269d..e217335a9b 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o +obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c new file mode 100644 index 0000000000..b5fc61c038 --- /dev/null +++ b/drivers/clk/sunxi/clk_a10s.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a10s_clk_priv { + void *base; +}; + +static int a10s_clk_enable(struct clk *clk) +{ + struct a10s_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB_OTG: + case CLK_AHB_EHCI: + case CLK_AHB_OHCI: + setbits_le32(priv->base + 0x60, BIT(clk->id - CLK_AHB_OTG)); + return 0; + case CLK_USB_OHCI: + setbits_le32(priv->base + 0xcc, BIT(6)); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + setbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int a10s_clk_disable(struct clk *clk) +{ + struct a10s_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB_OTG: + case CLK_AHB_EHCI: + case CLK_AHB_OHCI: + clrbits_le32(priv->base + 0x60, BIT(clk->id - CLK_AHB_OTG)); + return 0; + case CLK_USB_OHCI: + clrbits_le32(priv->base + 0xcc, BIT(6)); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + clrbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops a10s_clk_ops = { + .enable = a10s_clk_enable, + .disable = a10s_clk_disable, +}; + +static int a10s_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int a10s_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct a10s_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id a10s_clk_ids[] = { + { .compatible = "allwinner,sun5i-a10s-ccu" }, + { .compatible = "allwinner,sun5i-a13-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun5i_a10s) = { + .name = "sun5i_a10s_ccu", + .id = UCLASS_CLK, + .of_match = a10s_clk_ids, + .priv_auto_alloc_size = sizeof(struct a10s_clk_priv), + .ofdata_to_platdata = a10s_clk_ofdata_to_platdata, + .ops = &a10s_clk_ops, + .probe = a10s_clk_probe, + .bind = sunxi_clk_bind, +};