From patchwork Mon Jul 16 11:28:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 944340 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="cf4mKKGd"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ThSr5r9Mz9ryt for ; Mon, 16 Jul 2018 21:46:20 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 77F91C2210A; Mon, 16 Jul 2018 11:36:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6A50BC22073; Mon, 16 Jul 2018 11:30:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 437DFC2212F; Mon, 16 Jul 2018 11:29:56 +0000 (UTC) Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) by lists.denx.de (Postfix) with ESMTPS id CC91AC22073 for ; Mon, 16 Jul 2018 11:29:50 +0000 (UTC) Received: by mail-pg1-f195.google.com with SMTP id z14-v6so1094629pgv.12 for ; Mon, 16 Jul 2018 04:29:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Pq3/2WdQiokbk/WX9Qr1W+Ungc7CRn1viRFuerp7DsA=; b=cf4mKKGd9xPa7bSM72R3U5tOGfLuGMt5Uv0hlVW56N6i0nyczJU54cZq1emPVG44QJ KlMQVl2GaeR+mpOJn9dHg3H4iQYjKneqP9+LWLwjJRket+IL+yuToiD+9y48/z9UlntH iqebSsowoDO6fiTjkDhekTPNJQR2CnjDotL8k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Pq3/2WdQiokbk/WX9Qr1W+Ungc7CRn1viRFuerp7DsA=; b=Ct3U3QYb6Pkz7LalZAJt/clmul1++5cefNLB/AbMBuI21F5Ssgk9k5qicZ6LmPJPL7 AwwpLcGXCtOwOLWgeQa3V8ZV0Z0I8d4v4PJriuh/vPRdE5EfyCsBMhYyEQzohTs4DZW7 u0infgytYrxvCMq8B+eC1vDgCkHc8QDPeFZD2wLnNreAz72A7bi52GALmUFh2vsFlVTp 3FEpbNa+2pUxUiCKhG3O3YwL9iM1chlOW2SOheTR00pNtDoi36MB78Kxj9B/B8Y0sSuO jNNudlyl3hdy5qmdqbq91zQek5HrQ97X5kUqBy2+E9RcDpRu9YzFxiN08g7NwZT03uXh SW4Q== X-Gm-Message-State: AOUpUlE1hOsw9/cLYzpXgdry8PER2SgUdsb8EYdFrvdrxGVgr1/bDm2h eszKfb7Ge/ZPIAkmcQ0cQHzXRQ== X-Google-Smtp-Source: AAOMgpcQadEqST/WcLHG+YvSJ512X+lhcX7bzYc12CF5IC29++QYZdONuQBMeGw7Wxs+DNqIVQWHRw== X-Received: by 2002:a63:6345:: with SMTP id x66-v6mr15487965pgb.43.1531740589426; Mon, 16 Jul 2018 04:29:49 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.161]) by smtp.gmail.com with ESMTPSA id u9-v6sm20817464pfi.4.2018.07.16.04.29.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 04:29:49 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara Date: Mon, 16 Jul 2018 16:58:32 +0530 Message-Id: <20180716112850.3961-18-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [RFC 17/35] clk: sunxi: Add initial CLK driver for H3_H5 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial clock driver Allwinner for H3_H5. Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 7 ++ drivers/clk/sunxi/Makefile | 2 + drivers/clk/sunxi/clk_h3.c | 131 +++++++++++++++++++++++++++++++++++++ 3 files changed, 140 insertions(+) create mode 100644 drivers/clk/sunxi/clk_h3.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 3a86c91e75..065cadf2fe 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -8,6 +8,13 @@ config CLK_SUNXI if CLK_SUNXI +config CLK_SUN8I_H3 + bool "Clock driver for Allwinner H3/H5" + default MACH_SUNXI_H3_H5 + help + This enables common clock driver support for platforms based + on Allwinner H3/H5 SoC. + config CLK_SUN50I_A64 bool "Clock driver for Allwinner A64" default MACH_SUN50I diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 860bb6dfea..37e6bcb147 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -5,4 +5,6 @@ # obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o + +obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c new file mode 100644 index 0000000000..e924017717 --- /dev/null +++ b/drivers/clk/sunxi/clk_h3.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct h3_clk_priv { + void *base; +}; + +static int h3_clk_enable(struct clk *clk) +{ + struct h3_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_BUS_OTG: + case CLK_BUS_EHCI0: + case CLK_BUS_EHCI1: + case CLK_BUS_EHCI2: + case CLK_BUS_EHCI3: + case CLK_BUS_OHCI0: + case CLK_BUS_OHCI1: + case CLK_BUS_OHCI2: + case CLK_BUS_OHCI3: + setbits_le32(priv->base + 0x60, + BIT(23 + (clk->id - CLK_BUS_OTG))); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + case CLK_USB_PHY2: + case CLK_USB_PHY3: + setbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_OHCI2: + case CLK_USB_OHCI3: + setbits_le32(priv->base + 0xcc, + BIT(16 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int h3_clk_disable(struct clk *clk) +{ + struct h3_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_BUS_OTG: + case CLK_BUS_EHCI0: + case CLK_BUS_EHCI1: + case CLK_BUS_EHCI2: + case CLK_BUS_EHCI3: + case CLK_BUS_OHCI0: + case CLK_BUS_OHCI1: + case CLK_BUS_OHCI2: + case CLK_BUS_OHCI3: + clrbits_le32(priv->base + 0x60, + BIT(23 + (clk->id - CLK_BUS_OTG))); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + case CLK_USB_PHY2: + case CLK_USB_PHY3: + clrbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_OHCI2: + case CLK_USB_OHCI3: + clrbits_le32(priv->base + 0xcc, + BIT(16 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops h3_clk_ops = { + .enable = h3_clk_enable, + .disable = h3_clk_disable, +}; + +static int h3_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int h3_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct h3_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id h3_clk_ids[] = { + { .compatible = "allwinner,sun8i-h3-ccu" }, + { .compatible = "allwinner,sun50i-h5-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_h3) = { + .name = "sun8i_h3_ccu", + .id = UCLASS_CLK, + .of_match = h3_clk_ids, + .priv_auto_alloc_size = sizeof(struct h3_clk_priv), + .ofdata_to_platdata = h3_clk_ofdata_to_platdata, + .ops = &h3_clk_ops, + .probe = h3_clk_probe, + .bind = sunxi_clk_bind, +};