From patchwork Wed Jul 11 15:25:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 942571 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41Qjts5qqVzB4MV for ; Thu, 12 Jul 2018 01:40:05 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 61C4FC21F68; Wed, 11 Jul 2018 15:36:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id F1A6FC21E49; Wed, 11 Jul 2018 15:26:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 81552C21F93; Wed, 11 Jul 2018 15:26:09 +0000 (UTC) Received: from mail.bootlin.com (mail.bootlin.com [62.4.15.54]) by lists.denx.de (Postfix) with ESMTP id 291C7C21C51 for ; Wed, 11 Jul 2018 15:26:01 +0000 (UTC) Received: by mail.bootlin.com (Postfix, from userid 110) id DD729207AB; Wed, 11 Jul 2018 17:26:00 +0200 (CEST) Received: from localhost.localdomain (AAubervilliers-681-1-12-56.w90-88.abo.wanadoo.fr [90.88.133.56]) by mail.bootlin.com (Postfix) with ESMTPSA id 2E99020943; Wed, 11 Jul 2018 17:25:38 +0200 (CEST) From: Miquel Raynal To: Daniel Schwierzeck , Scott Wood , Jagan Teki Date: Wed, 11 Jul 2018 17:25:29 +0200 Message-Id: <20180711152529.24547-22-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180711152529.24547-1-miquel.raynal@bootlin.com> References: <20180711152529.24547-1-miquel.raynal@bootlin.com> Cc: Tom Rini , Alexandre Belloni , Boris Brezillon , Antoine Tenart , Allan Nielsen , u-boot@lists.denx.de, Miquel Raynal , Stefan Roese Subject: [U-Boot] [PATCH v2 21/21] dt-bindings: Add bindings for SPI NAND devices X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Boris Brezillon Add bindings for SPI NAND chips. Signed-off-by: Boris Brezillon Signed-off-by: Miquel Raynal --- doc/device-tree-bindings/mtd/spi-nand.txt | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 doc/device-tree-bindings/mtd/spi-nand.txt diff --git a/doc/device-tree-bindings/mtd/spi-nand.txt b/doc/device-tree-bindings/mtd/spi-nand.txt new file mode 100644 index 0000000000..d55f80196c --- /dev/null +++ b/doc/device-tree-bindings/mtd/spi-nand.txt @@ -0,0 +1,27 @@ +SPI NAND flash + +Required properties: +- compatible: should be "spi-nand" +- reg: should encode the chip-select line used to access the NAND chip + +Optional properties +- spi-max-frequency: maximum frequency of the SPI bus the chip can operate at. + This should encode board limitations (i.e. max freq can't + be achieved due to crosstalk on IO lines). + When unspecified, the driver assumes the chip can run at + the max frequency defined in the spec (information + extracted chip detection time). +- spi-tx-bus-width: The bus width (number of data wires) that is used for MOSI. + Only encodes the board constraints (i.e. when not all IO + signals are routed on the board). Device constraints are + extracted when detecting the chip, and controller + constraints are exposed by the SPI mem controller. If this + property is missing that means no constraint at the board + level. +- spi-rx-bus-width: The bus width (number of data wires) that is used for MISO. + Only encodes the board constraints (i.e. when not all IO + signals are routed on the board). Device constraints are + extracted when detecting the chip, and controller + constraints are exposed by the SPI mem controller. If this + property is missing that means no constraint at the board + level.