From patchwork Sun May 6 14:25:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Marty E. Plummer" X-Patchwork-Id: 909311 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=startmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=startmail.com header.i=@startmail.com header.b="jzpvaFCJ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40f7PY42Ltz9s1d for ; Mon, 7 May 2018 00:27:29 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2EA00C21FD0; Sun, 6 May 2018 14:26:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 45CF9C21FB4; Sun, 6 May 2018 14:25:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AAFE9C21FBD; Sun, 6 May 2018 14:25:40 +0000 (UTC) Received: from mx-out1.startmail.com (mx-out1.startmail.com [145.131.90.139]) by lists.denx.de (Postfix) with ESMTPS id EAD1CC21FB8 for ; Sun, 6 May 2018 14:25:36 +0000 (UTC) From: "Marty E. Plummer" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=startmail.com; s=2017-11; t=1525616736; bh=iOh7F3Ycy9BjkQaQ74tLGIBzO/hAG6Lf9fbx3c9qqHQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jzpvaFCJ2SC278wMtB9iabD1Yj2ySK7cXoch3ONhF9TZE/lNtZbpSAVW1+R9UOr+L /ojfIS3nHlVa5ntLeaUU5y/UTo1Pc+jQA5hIRKUW/afaRzDw6CPum0wIwU7oaU6gIC b3HG4slL6KXrN/3VhD3TN32NFdGA7h9MA/tWb8T19TeBHRRCQjYH7OXa/NaewdpLXb 9OJ3vP4EHiBXo1LHawhel+pbF1RfBFJ8CrzhicK5RhCeO4Rnt2yD/iEC3LV4BdrT8Y Jj2DLfUg22CAlp8t0j/rOeu2SuGCF8IyVYoHSDQs3jx5/xg52lj8FML69xeNwQNoGH A1EQr2XF3ZtVg== To: u-boot@lists.denx.de Date: Sun, 6 May 2018 09:25:13 -0500 Message-Id: <20180506142513.19911-4-hanetzer@startmail.com> In-Reply-To: <20180506142513.19911-1-hanetzer@startmail.com> References: <20180506142513.19911-1-hanetzer@startmail.com> Cc: vagrant@debian.org, linux-rockchip@lists.infradead.org, "Marty E. Plummer" Subject: [U-Boot] [PATCH 3/3] rockchip: fix incorrect detection of ram size X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Taken from coreboot's src/soc/rockchip/rk3288/sdram.c Without this change, my u-boot build for the asus c201 chromebook (4GiB) is incorrectly detected as 0 Bytes of ram. Signed-off-by: Marty E. Plummer --- arch/arm/mach-rockchip/sdram_common.c | 62 ++++++++++++++++----------- 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index 76dbdc8715..a9c9f970a4 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; size_t rockchip_sdram_size(phys_addr_t reg) @@ -19,34 +21,44 @@ size_t rockchip_sdram_size(phys_addr_t reg) size_t size_mb = 0; u32 ch; - u32 sys_reg = readl(reg); - u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) - & SYS_REG_NUM_CH_MASK); + if (!size_mb) { - debug("%s %x %x\n", __func__, (u32)reg, sys_reg); - for (ch = 0; ch < ch_num; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & - SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & - SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & - SYS_REG_CS1_ROW_MASK); - bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK)); - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; + u32 sys_reg = readl(reg); + u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) + & SYS_REG_NUM_CH_MASK); - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + debug("%s %x %x\n", __func__, (u32)reg, sys_reg); + for (ch = 0; ch < ch_num; ch++) { + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & + SYS_REG_RANK_MASK); + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK); + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK); + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & + SYS_REG_ROW_3_4_MASK; - if (rank > 1) - chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); - if (row_3_4) - chipsize_mb = chipsize_mb * 3 / 4; - size_mb += chipsize_mb; - debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", - rank, col, bk, cs0_row, bw, row_3_4); + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + + if (rank > 1) + chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); + if (row_3_4) + chipsize_mb = chipsize_mb * 3 / 4; + size_mb += chipsize_mb; + debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", + rank, col, bk, cs0_row, bw, row_3_4); + } + + /* + * we use the 0x00000000~0xfeffffff space + * since 0xff000000~0xffffffff is soc register space + * so we reserve it + */ + size_mb = min(size_mb, 0xff000000/SZ_1M); } return (size_t)size_mb << 20;