From patchwork Wed Mar 7 21:52:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882812 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="YkKqWQ+C"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSDd140Gz9sgw for ; Thu, 8 Mar 2018 08:57:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C6AFDC21E68; Wed, 7 Mar 2018 21:56:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D1BAFC21F24; Wed, 7 Mar 2018 21:55:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C4A9EC21E57; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 82BB4C21E62 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 3E0D862643; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=9jwAxYZK9zXsWOmeGnsyvNabZVAck9NA25aUHtj6MsI=; h=From:To:Date; b=YkKqWQ+CEbvW22kKDBv+5+jLcV9vTfMXtRTvYLo9Ehbk7I18vXxg3iBzIRUDd2MwB 54ExEGSEeTr8lMCUlXYiLxzNtLW9Ug4OdcCI8IPLimxb2sHqDvaKkQ5nTA3Yk0zPQT 061fD2ru8YmFAs6w6uenBjdkbq4yHRos9k74r/AA= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:03 +0100 Message-Id: <20180307215216.10418-7-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 06/19] phy: marvell: a3700: Use reg_set_indirect istead of 2 reg_sets X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Create a special function for indirect register setting, reg_set_indirect, and use it instead of the two calls to reg_set. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 734d4e55b1..81d24a5b61 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -224,6 +224,17 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) return ret; } +/* + * reg_set_indirect + * + * return: void + */ +static inline void reg_set_indirect(u32 reg, u16 data, u16 mask) +{ + reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF); + reg_set(rh_vsreg_data, data, mask); +} + /* * comphy_sata_power_up * @@ -231,43 +242,40 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) */ static int comphy_sata_power_up(void) { - int ret; + int ret; debug_enter(); /* * 0. Swap SATA TX lines */ - reg_set(rh_vsreg_addr, vphy_sync_pattern_reg, 0xFFFFFFFF); - reg_set(rh_vsreg_data, bs_txd_inv, bs_txd_inv); + reg_set_indirect(vphy_sync_pattern_reg, bs_txd_inv, bs_txd_inv); /* * 1. Select 40-bit data width width */ - reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); - reg_set(rh_vsreg_data, 0x800, bs_phyintf_40bit); + reg_set_indirect(vphy_loopback_reg0, 0x800, bs_phyintf_40bit); /* * 2. Select reference clock and PHY mode (SATA) */ - reg_set(rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF); if (get_ref_clk() == 40) { - reg_set(rh_vsreg_data, 0x3, 0x00FF); /* 40 MHz */ + /* 40 MHz */ + reg_set_indirect(vphy_power_reg0, 0x3, 0x00FF); } else { - reg_set(rh_vsreg_data, 0x1, 0x00FF); /* 25 MHz */ + /* 20 MHz */ + reg_set_indirect(vphy_power_reg0, 0x1, 0x00FF); } /* * 3. Use maximum PLL rate (no power save) */ - reg_set(rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF); - reg_set(rh_vsreg_data, bs_max_pll_rate, bs_max_pll_rate); + reg_set_indirect(vphy_calctl_reg, bs_max_pll_rate, bs_max_pll_rate); /* * 4. Reset reserved bit (??) */ - reg_set(rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF); - reg_set(rh_vsreg_data, 0, bs_phyctrl_frm_pin); + reg_set_indirect(vphy_reserve_reg, 0, bs_phyctrl_frm_pin); /* * 5. Set vendor-specific configuration (??)